Theory Of Operation; Dma Turbo - Atmel AT91 Series Application Note

Theory of Operation

The principle of DMA is that an external event causes a fast memory copy. In this case the external event is the Fast Inter-
rupt pin (FIQ) since the FIQ mode on the ARM7TDMI
saved before being used in FIQ mode. These registers are initialized before enabling the FIQ interrupt, then directly used
when the external event occurs.
This application note describes two ways to implement a software DMA. Both implementations make the transfer by split-
ting the block to be transferred into packets of 4 words.
Note: In this document 1 packet = 4 words; 1 word = 4 bytes
• DMA Turbo: Copies one packet (4 words) from a source buffer to a destination buffer at each FIQ interrupt.
• DMA Channel: Copies the number of packets (4 words) defined by the user from a source buffer to a destination buffer
at each FIQ interrupt, thus freeing the core between packets.
As the FIQ interrupt is used, the DMA must be able to access the banked registers. This can only be done by switching to
FIQ mode and only if the CPU is in privileged state (any mode except User Mode). This application note assumes that the
user function calls are performed while the CPU is in privileged state. It does not describe how to switch from unprivileged
to privileged state. This can be done on another level by using the "swi" instruction of the ARM core or the Advanced Inter-
rupt Controller features allowing an interrupt entry to be forced. In the last case, FIQ or AIC's software interrupt can be
forced to set up software DMA.
Table 1. Source Files
Files Contents
dma _turb.s Code source for DMA Turbo
dma_chnl.s Code source for DMA channel
dma.h DMA prototypes and structures for application use
arm.inc ARM core definition

DMA Turbo

The DMA Turbo allows 1 packet (4 words) to be transferred at each FIQ interrupt from a source buffer to a destination
buffer. Source and destination buffer pointers are post-incremented after each transfer.
The main advantage to this implementation is that no registers need to be saved. It is also a faster way to transfer data than
the DMA Channel implementation.
Table 2. Registers Used
Register Parameter
r14 Link register - return address
r13 'dest_pt' = Destination buffer pointer
r12 'src_pt' = Source buffer pointer
r8 to r11 Transfer registers
AT91 Series
2
™
processor has banked registers (r8 to r14) which do not need to be