Table of Contents
Advertisement
Firmware
Primary Booter
Resources Used by the Primary Booter
PPC/PMC-8260/DS1
The primary booter contains tools for:
•
Loading software via PCI bus
•
Programming the flash
•
Accessing on-board resources
•
Reporting POST result information to the host
For this purpose a simple communication protocol is implemented. On the follow-
ing pages this communication protocol with its commands, return codes, and the
I/O buffer are described. The end of this section provides instructions on how to
program routines for using the primary booter.
As can be seen in the following figure, the primary booter code is located within
the main memory (SDRAM). 256 byte of main memory are used as control and sta-
tus register section (CSR) which is used for the communication protocol. The CSR
section is accessible both from the PCI bus (via the default base translation register
provided by the PCI bridge) and the local PowerQUICC II.
The BST0 register of the PowerSpan II PCI bridge is configured to 4 MByte by
hardware. The primary booter maps this window to the last 4 MByte of local
SDRAM. The PCI memory address is assigned by the PCI bus enumerator of the
host.
The following figure shows the memory layout as seen from the local CPU (right)
and the PCI bus (left). The SDRAM and SSRAM regions marked by the dashed
lines are not directly accessible from PCI bus. In order to read from/write to these
regions, the contents must first be copied into the I/O buffer area (see shaded area
in the following figure).
Loading Application Software
4 - 15
Advertisement
Table of Contents
