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Ultra DMA timing parameters
t
Unlimited interlock time
UI
Maximum time allowed for output drivers to
t
AZ
release (from being asserted or negated)
t
Minimum delay time required for output
ZAH
drivers to assert or negate (from released
t
ZAD
state)
Envelope time (from DMACK- to STOP and
t
ENV
HDMARDY- during data out burst initiation)
Ready-to-final-STROBE time (no STROBE
t
edges shall be sent this long after negation
RFS
of DMARDY-)
Ready-to-pause time (time that recipient
t
shall wait to initiate pause after negating
RP
DMARDY-)
Pull-up time before allowing IORDY to be
t
IORDYZ
released
Minimum time device shall wait before
t
ZIORDY
driving IORDY
Setup and hold times for DMACK- (before
t
ACK
assertion or negation)
Time from STROBE edge to negation of
t
DMARQ or assertion of STOP (when
SS
sender terminates a burst)
80000-FLD25-xxx(M/G)UH1(I)-March2011
Mode 0
Mode 1
Min.
Max.
Min.
Max.
Min.
0
-
0
-
-
10
-
10
20
-
20
-
20
0
-
0
-
20
70
20
70
20
-
75
-
70
160
-
125
-
100
-
20
-
20
0
-
0
-
20
-
20
-
20
50
50
-
50
QDFLD25‐xxx(M/G)UH1(I)
Mode 2
Mode 3
Mode 4
Max.
Min.
Max.
Min.
0
-
0
-
0
-
10
-
10
-
-
20
-
20
0
-
0
-
0
70
20
55
20
-
60
-
60
-
-
100
-
100
-
20
-
20
-
0
-
0
-
0
-
20
-
20
-
20
-
20
Datasheet
Max.
-
10
-
-
55
60
-
20
-
-
-
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