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PIO timing parameters
t
Cycle time (min.)
0
t
Address valid to HIOR-/HIOW- setup (min.)
1
t
HIOR-/HIOW- 16-bit (min.)
2
t
HIOR-/HIOW- Register 8-bit (min.)
2
t
HIOR-/HIOW- recovery time (min.)
2i
t
HIOW- data setup (min.)
3
t
HIOW- data hold (min.)
4
t
HIOR- data setup (min.)
5
t
HIOR- data hold (min.)
6
t
HIOR- data tri-state (max.)
6z
t
Address valid to IOCS16- assertion (max.)
7
t
Address valid to IOCS16- released (max.)
8
t
HIOR-/HIOW- to address valid hold
9
t
Read data valid to IORDY active (min.)
RD
t
IORDY setup time
A
t
IORDY pulse width (max.)
B
t
IORDY assertion to release (max.)
C
Multiword DMA
80000-FLD25-xxx(M/G)UH1(I)-March2011
Table 13: Read/Write Timing Specifications, PIO Mode 0-4
Figure 5: Read/Write Timing Diagram, Multiword DMA Mode
QDFLD25‐xxx(M/G)UH1(I)
Mode 0
Mode 1
Mode 2
600
383
240
70
50
30
165
125
100
290
290
290
-
-
-
60
45
30
30
20
15
50
35
20
5
5
5
30
30
30
90
50
40
60
45
30
20
15
10
0
0
0
35
35
35
1250
1250
1250
5
5
5
Datasheet
Mode 3
Mode 4
180
120
30
25
80
70
80
70
70
25
30
20
10
10
20
20
5
5
30
30
n/a
n/a
n/a
n/a
10
10
0
0
35
35
1250
1250
5
5
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