Table of Contents
Advertisement
Figure 9: Sustained Ultra DMA Mode Data-out Burst Timing Diagram
Ultra DMA timing parameters
t
Typical sustained average two cycle time
2CYC
Cycle time allowing for asymmetry and
t
clock variations (from STROBE edge to
CYC
STROBE edge)
Two cycle time allowing for clock variations
(from rising edge to next rising edge or from
t
2CYC
falling edge to next falling edge of
STROBE)
t
Data setup time (at recipient)
DS
t
Data hold time (at recipient)
DH
Data valid setup time at sender (from data
t
DVS
bus being valid until STROBE edge)
Data valid hold time at sender (from
t
STROBE edge until data may become
DVH
invalid)
First STROBE time (for device to first
t
negate DSTROBE from STOP during a data
FS
in burst)
Ultra DMA timing parameters
t
Limited interlock time
LI
t
Interlock time with minimum
MLI
80000-FLD25-xxx(M/G)UH1(I)-March2011
Table 15: Timing Diagram, Ultra DMA Mode 0-4
Mode 0
Min.
Max.
240
-
112
-
230
-
15
-
5
-
70
-
6.2
-
-
230
Mode 0
Min.
Max.
0
150
20
-
Mode 1
Mode 2
Min.
Max.
Min.
Max.
Min.
160
-
120
-
90
73
-
54
-
39
153
-
115
-
86
10
-
7
-
5
-
5
-
48
-
31
-
20
6.2
-
6.2
-
6.2
-
200
-
170
Mode 1
Mode 2
Min.
Max.
Min.
Max.
Min.
0
150
0
150
20
-
20
-
20
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
Mode 3
Mode 4
Max.
Min.
Max.
-
60
-
-
25
-
-
57
-
7
-
5
-
5
-
5
-
-
6.7
-
-
6.2
-
-
130
-
120
Mode 3
Mode 4
Max.
Min.
Max.
0
100
0
100
-
20
-
- 14 -
Advertisement
Table of Contents
