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Table 14: Read/Write Timing Specifications, Multiword DMA Mode 0-2
Multiword DMA timing parameters
t
Cycle time (min.)
0
t
HIOR-/HIOW- assertion width (min.)
D
t
HIOR- data access (max.)
E
t
HIOR- data hold (min.)
F
t
HIOR-/HIOW- data setup (min.)
G
t
HIOW- data hold (min.)
H
t
DMACK to HIOR-/HIOW- setup (min.)
I
t
HIOR-/HIOW- to DMACK hold (min.)
J
t
HIOR- negated width (min.)
KR
t
HIOW- negated width (min.)
KW
t
HIOR- to DMARQ delay (max.)
LR
t
HIOW- to DMARQ delay (max.)
LW
t
CS1-, CS0- valid to HIOR-/HIOW-
M
t
CS1-, CS0- hold
N
t
DMACK-
Z
Ultra DMA mode
Figure 6: Ultra DMA Mode Data-in Burst Initiation Timing Diagram
80000-FLD25-xxx(M/G)UH1(I)-March2011
QDFLD25‐xxx(M/G)UH1(I)
Mode 0
Mode 1
480
150
215
80
150
60
5
5
100
30
20
15
0
0
20
5
50
50
215
50
120
40
40
40
50
30
15
10
20
25
Datasheet
Mode 2
120
70
50
5
20
10
0
5
25
25
35
35
25
10
25
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