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DMACK
29
31
INTRQ
HAB[1]
33
35
HAB[0]
37
CS0
39
DASP
41
VCC
43
GND
In the 44-pin version, this pin is defined as KEY, according to the ATA standard.
NC = These pins are not connected internally.
Signal usage in PIO & Multiword DMA mode.
Signal usage in Ultra DMA mode.
3.3.
Electrical Description
The Industrial 2.5" PATA (IDE) SSD is optimized for operation with hosts. Table 8 describes the signals of 44-pin IDE
interface.
Pin No.
Signal Name
1
HRESET-
37
CS0-
38
CS1-
31
INTRQ
3
HIOR-
4
HDMARDY-
25
4
HSTROBE
3
HIOW-
23
4
STOP
32
IOCS16-
3
IORDY
4
27
DDMARDY-
4
DSTROBE
18, 16, 14, 12,
10, 8, 6, 4, 3,
HDB[15:0]
5, 7, 9, 11, 13,
15, 17
33, 35, 36
HAB[2:0]
28
CSEL- I
DASP-
39
80000-FLD25-xxx(M/G)UH1(I)-March2011
DMA Acknowledge
Interrupt Request
Host Address Bit 1
Host Address Bit 0
Chip Select 0
Drive Active
Supply Voltage
Ground
Table 8: Signal Description
Type
I
Host reset signal, High: Reset.
I
Chip select CS0
I
Chip select CS1
O
Host interrupt signal.
I/O read strobe signal.
DMA ready during Ultra DMA data in burst
I
Data strobe during Ultra DMA data out burst
I/O write strobe signal.
I
Stop during Ultra DMA data bursts
O
Asserted in 16-bit access.
I/O Ready Signal
O
DMA ready during Ultra DMA data out burst
Data strobe during Ultra DMA data in burst
I/O
Host data bus
Host Address bus
I/O
Master/Slave select signal (cable select signal).
Low: Device operates as a master, High: Device operates as a slave.
I
Switch used.
Used as an input port to check in the master mode to see if the slave
I/O
is present or not, and as an output port to check in the slave mode to
see if the slave for the master is present or not.
GND
Ground
30
32
IOCS16
CS I/O 16-Bit
PDIAG
Passed Diagnostic
34
36
HAB[2]
Host Address Bit 2
38
CS1
Chip Select 1
40
GND
Ground
42
VCC
Supply Voltage
2
44
NC
Not Connected
Description
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
- 8 -
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