HP 5065A Operating And Service Manual page 94

Model 5065A
Circuit Diagrams, Theory, and Maintenance
CHANGE 13 (968):
Page 8-31, Figure 8-18, A8 PHASE DETECTOR
Assembly:
Change A1 to Q3, Q8 to Q11 to 1854-0003.
Page 6-11, Table 6-2:
Change A8Q1 to A8Q3 and A8Q8 to A8Q11 to
1854-0003.
When the regenerative division process starts, the start
circuit is no longer required. A small sample of the
100 kHz output connects to CR3 and CR5 to produce a
negative bias to cut off Q7. The resulting increased
voltage at Q4 emitter cuts this stage off, which in turn
positively biases FET switch "off" to open the start
oscillator path. The regenerative dividing process is
maintained as long as there is continuity in the 1 MHz
input.
The A4 Module uses regenerative division to divide 1
MHz to 100 kHz as shown. Operation is similar to that
of A7 1 MHz Frequency Divider.
Figure 7-3. 100 kHz Regenerative Divider
900KHI ^v^ J-«
± ,' > START
i t ' i osc
lOOKHz
- * - lOOKHz
m
The 100 kHz divider is a regenerative divide-by-ten cir­
cuit followed by an amplifier stage. This assembly in­
cludes signal-sensing logic to control the divider-start
circuit in response to both the 100 kHz output and the
dc start signal that comes from A7 1 MHz Frequency
Divider. Assume the 1 MHz signal is present at the
divider circuit input, but the 100 kHz output has not
started. Divider operation requires 100 kHz at the base
of Q3, the X9 multiplier. This 100 kHz signal is
derived from the output signal once the divider starts.
During divider start, the required 100 kHz signal is
obtained by converting tuned amplifier A6 into a 100
kHz oscillator by feeding a signal from its output back
to its input through FET switch Q5.
The 1 MHz signal input to A4 is amplified by Q1. The
input is also coupled through Q2 whose output connects
through A4(2) to A5 Digital Divider. The start signal
connects from A6 1 MHz Frequency Divider through
A4(4) to Q4; Q4 biases Q5 "on" to complete the feed­
back path for Q7 which then oscillates at 100 kHz.
Multiplier stage Q3 converts 100 kHz at its base to 900
kHz in its tuned collector circuit. The resulting 900
kHz mixes with the input 1 MHz from T1 in mixing
diode CR2. The parallel resonance of l_3 and C8, tuned
to 100 kHz, traps all undesired frequencies in the mixing
product. 100 kHz couples to Q7 to complete the re-
genative path.
Q9 and Q10 feed the 100 kHz front and rear panel out­
put jacks. Adjustable T3 tunes Q10 for optimum power
out. A second 100 kHz output is supplied by clock
amplifier Q8 through A4()14). Diode CR5 and C29 in
T3 output provide a rectified and filtered dc output for
the 100 kHz position of the CIRCUIT CHECK meter.
A4 MAINTENANCE
NORMAL OPERATION
The A4 circuits process the A6 1 MHz output by
means of regenerative division to produce 100 kHz. The
A4 Assembly starts dividing when both 1 MHz and the
dc start signal from A6 are present at A4 inputs. A4
outputs are as follows:
a. 100 kHz to front and rear-panel jacks from
A4(11).
b. A buffer amplifier 1 MHz output to A5 Digital
Divider Assembly from A4(2).
c. Rectified 100 kHz output to CIRCUIT CHECK
meter from A4(15).
d. A separate rear panel CLOCK 100 kHz output
from A4(14).
OPERATIONAL CHECK
a. A simple check of A4 operation can be made by
observing the CIRCUIT CHECK 100 kHz indication and
comparing it with the reference meter readings on the
front-panel door. In addition, the rear-panel CLOCK
100 kHz output should be 1 volt rms into 1000 ohms;
also, the 1 MHz buffer amplfiier output at A4(2) should
be .5 volts rms into 1000 ohms.
7-8