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Model 5065A
Circuit Diagrams, Theory, and Maintenance
CLOCK DISPLAY ASSEMBLY A19
The digital clock is a solid-state 24 hour clock with a seven
segment LED (light emitting diode) display. It indicates
time in hours, minutes, and seconds in synchronism with
the 5065A generated 1 PPS signal. Time may be set and
synchronized using the HOLD, SLOW/FAST, and SET
switches.
The required inputs which enable the clock to operate are
connected to the clock by five wires. These are:
1. Unregulated +28Vdc from the 5065A used to generate a
regulated+5Vdc,and used exclusively to drive the display.
2. Regulated +12Vdc from the A5 assembly used exclu
sively to operate the CMOS circuits in the display.
3. 1 PPS signal from the 5061A used to synchronize the
clock and increment the display.
4. AC line sense signal from A2(9)
turns off the display
portion if instrument AC power fails or is removed. To
display time, when AC power is not available, the clock
front-panel STANDBY READ must be pressed.
5. 1 PPS and 12Vdc common. Circuit ground connects to
the chassis through the LED digital clock circuits.
Two circuit boards make up the A19 Clock Display: the
A19A1, Regulator/Driver (located at the rear of the A19
Assembly), and the A19A2, Display board.
A19A1 REGULATOR/DRIVER, GENERAL
The A19A1 Assembly contains two separate circuits. The
regulator portion takes the unregulated 28Vdc from the
5065A and regulates it down to +5Vdc to provide powerfor
the display light-emitting diodes. The driver portion takes
the 1 PPS signal from the 5065A and shapes it for use by the
clock accumulator/driver ship on A19A2. These two sepa
rate circuits are described in the following paragraphs
under appropriate headings.
The regulator portion of the A19A1 Assembly consists of
U2, Q3, Q4 and associated components. U2 is a switching
regulator circuit that contains the switching oscillator, vol
tage reference, and switching transistordrivecircuitry. The
+ 5V regulator output voltage is sampled through R13 at
U2(1). This voltage is compared to the reference input at
U2(2). U1 adjusts the amount of time Q3 conducts based on
whether the output voltage ( + 5V) is too high or too low.
C9, L1, and C10 form a filter to keep switching transients
out of the 5065A power supply. R9 and C7 set the switching
frequency of the regulator. U2 provides a regulated +5Vdc
at pin 16. This voltage provides the reference as well as
providing power for Q2. L2 keeps current flowing to the
load when Q3 is off. C14 and C15 filter the +5Vdc output.
The circuitry of Q2 turns off the power supply to conserve
power when the 5065A is operating from battery power.
Under normal operation, when ac power is applied, zener
diode CR1 conducts turning on Q2. This allows U2 to oper
ate normally. When ac power is lost, Q2 turns off, forward
biasing CR2 which in turn prevents the power supply from
operating.
Pressing the STANDBY READ switch enables power supply
operation, lighting the display. Current limiting and over-
voltage protection is provided by Q4 and CR3, respectively.
The Clock Driver portion of the A19A1 Assembly operate
in the following manner. A short (150 nsec) low level puls
(=1V) is applied to the input of Q1 from A16A1 (WHT
This pulse is amplified (by Q1) and shaped by 555 timer U*
The output of U1 goes to A17A2 where it drives the cloc
accumulator/display IC. In normal operation U1 behaves-
like a one-shot multivibrator outputting one pulse for each
input pulse. When the SET pushbutton is activated, U1 free
runs, and generates a signal whose frequency is set by th
position of the SLOW/FAST switch. In SLOW, the fre^
quency is approximately 60 Hz, 600 Hz in FAST. These two
frequencies allow the hours, minutes, and seconds on th
display to be easily set.
_
A19A2, CLOCK DISPLAY BOARD
The clock display board consists of a MOS cloc
chip, a transistor array, a buffer amplifier array, four drive—
transistors, and six LED displays. This assembly's function
is to accumulate and display time-of-day in synchronisr
with the instrument's 1 PPS signal. Operation is as follow
The MOS circuit U1 normally operates from 50 or 60 Hz. It^-
enabled to operate by the 1 PPS signal from A19A1 by
grounding the "slow set" line at U1 (17). U1 divides the "
PPS input to form the hours, minutes, and seconds cour
In addition, it formats the output so that this count may tre-
displayed on a seven-segment strobed LED display.
The time display signals from U1 are composed of tv\
parts:
—
1. The digit enable signal
2. The multiplexed seven-segment signal
^
The digits enable signals from U1 are:
Pin 23: tens-of-hours.
Pin 24: units-of-hours.
—
Pin 25: tens-of-minutes.
Pin 26: units-of-minutes.
Pin 21: tens-of-seconds.
Pin 22: units-of-seconds.
—
These signals enable the LED displays through U3 gate
and allow the multiplexed seven segment outputs to turn (
the correct display segment.
—
The "segment enabling signals" are buffered through I ":
stages and applied to the LED displays. Thus, the segmer >
of an individual number display are enabled by outpurs
from U1 (6 to 12) while the display itself is turned on by one
of the U1 (21 to 26) outputs.
The multiplexed seven-segment signals from U1 are shown
below.
Legend:
Pin 6: for segment a.
Pin 7: for segment b.
Pin 8: for segment c.
Pin 9: for segment d.
Pin 10: for segment 3.
Pin 11: for segment f.
Pin 12: for segment g.
• / '
•LI
8-68
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