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Model 5065A
Circuit Diagrams, Theory, and Maintenance
Digital Divider Timing Diagrams
A 5 A 2
1C2 ( 1 0 )
GATED IMC
A5A2
I C 3 ( 7 )
IMC DRIVE
A 5 A 2
I C I 4 B ( 8 )
IPPS TICK
A 5 A 3
I C I 5 ( 7 )
RESET
A5A3
IC 16 ( 1 0 )
PRESET
A5A3
[ C I 7 B ( 7 )
6ATE
CONTROL
A 5 A 3
I C I 2 A ( 6 )
TW SET
( 0 0 0 0 0 1 )
A 5 A 3
I C i 2 A ( 6 )
TW SET
( 0 0 0 0 0 2 )
A 5 A 3
I C 2 D ( 6 )
TW SET
( 0 0 0 0 0 2 )
TO B
OSC OUT
A 5 A 3
1C2D ( 6 )
TW SET
( 0 0 0 0 0 1 )
TO B
OSC
OUT
!50nS
(Thumbwheel switch set at 000001)
rL_n_n_[i_p_
-W
\r^~v
Til
! 5 0 n S
-J
| 0.5 fJ.S
T
U
5 0
V V
\l
nS
~l
Jt
I I
I/J.S
I
I
1.3
flS
1
1/iS
'
(Thumbwheel switch set at 999999)
A 5 A 3
IC2 (10)
GATED IMC
A5A3
I C 3
( 7 )
I MC DRIVE
A5A3
I C I 4 B ( 8 )
IPPS
TICK
A 5 A 3
I C I 5 ( 7 )
RESET
A5A3
I C I 6 (10)
PRESET
A 5 A 3
I C I 7 B ( 7 )
GATE
CONTROL
A 5 A 3
ICI2A ( 6 ]
A 5 A 3
I C 2 D ( 6 )
TO B
OSC OUT
A 5 A 3
I C I 3 (10)
rL_p_n_n__n_
"itf
11
11
11
11
11
11
■ H -
I I
I I
I I
I I
"!tf
I I
I I
I I
I I
I I
I I
I I
150
150
nS —•>]
nS
U
^ T ^ ^
it
if
-\ k°
i—
1.3 f t S
l . l ^ i S
1
1.5 / i S
r
r
r
r
r
r
T
T
j
8-32
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