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Model 5065A
C i r c u i t D i a g r a m s , T h e o r y , and M a i n t e n a n c e
DIGITAL DIVIDER A5 THEORY
GENERAL DESCRIPTION
The A5 Digital Divider provides a one pulse-per-second
signal for a front and rear panel output signal, and
drives the A19 Clock Display Assembly. The 1 P P S
output can by synchronized to an external 1 P P S signal
with selectable time delay difference with respect to an
external synchronizing 1 P P S .
A5 has four subassemblies:
1. A5A1 Multiplier and Amplifier
2. A5A2 Voltage Regulator
3. A5A3 10 MHz-to-1 P P S Divider And Delay
4. A5A4 Interconnect
The four subassemblies are described in the following
paragraphs.
A5A1 Multiplier-Amplifier
The A5A1 Multiplier and Amplifier has three separate
parts: 1) a 1 MHz-to-10 MHz multiplier, 2) an amplifier,
and 3) a drive for the A19 Clock Display.
The multiplier section provides a 10 MHz output signal
generated from the 1 MHz input signal supplied by A6.
The 1 MHz signal, which comes in on the J4 RF
connector, is coupled through C l to the base of Ql. Ql,
which is part of the differential amplifier Q1-Q2, acts as
a switch. The input signal is switched through L2 to
generate 1 MHz harmonics. CRl prevents ringing in the
signal that could damage Q2 and Q3. The output of Q2 is
connected to Q3, which is a tuned amplifier at the
resonant frequency of LI a n d C4. The output of Q3 is
applied to another amplifier (Q4-Q5) tuned to 10 MHz by
L3. At this point, a good 10 MHz sine wave has been
generated. The output of Q5 is coupled through C10 to
the input of the sine wave-to-TTL converter, Q6-Q7.
When the signal is above the dc bias of Q6, Q6 switches
off, switching Q7 on. This generates a TTL-high pulse at
A~5A1(12) that follows the 10 MHz sine wave from Q5.
Diode CR2 produces the dc bias voltage for Ql, Q2, Q4,
Q5, Q6, and Q7.
The amplifier section of A5A1 h a s an amplifier that
converts the 1 PPS signal from A5A3 to TTL for the
front-panel 1 PPS output connectors. Transistors Q8,
Q9, and Q l l comprise this amplifier.
The third section of A5A1 h a s a single transistor
amplifier, Q14, that drives the A19 Clock Display with
the 1 P P S signal from A5A3. U l is a regulator that
transforms an input of +18 Volts to +12 Volt power for
the A16 Clock Display Assembly.
The A5A1 assembly is a connection point for signals
from the H P 5065A making them available for external
8 - 2 8
(SERIES 2340A)
use. Connector J4 has the 1 MHz input sine wave, at
about 1 Volt rms, that is applied to a 10 MHz multiplier.
The 10 MHz signal at ASAl(12) is connected through
A5A4 to A5A3TT2T. The SYNC signal from J12 on the
5065A rear panel is connected through A5A1 to A5A4
and then to A5A3(1). The 1 PPS signal from A5A3 is
synchronized with the SYNC signal from the 5065A rear
panel. The other R F connector, J l , is a 1 P P S output. T h e
1 PPS from A5A1J1 is connected to J13 on the 5065A
front panel. There are four terminals on A5A1. Terminal
4 is the +18 Volt input terminal and has a red wire
connected to it. Terminals 1, 2, and 3 are outputs to the
A19 Clock Display. Pin 1 is common (ground). Pin 2 is
the +12 Volt power. Pin 3 is the 1 P P S signal that drives
the front-panel clock display.
A5A2 5-Volt Regulator
The A5A2 assembly receives the +18 Volt power from
A5A1 and regulates it to +5 Volts for A5A1 and A5A3.
There are three basic circuits in A5A2:
1. voltage reference
2. switching regulator
3. short-circuit current protection
U3 is a voltage reference that supplies +2.5-Volt refer
ence to the non-inverting input [U2(2)] of the switching
regulator. Feedback from the regulator output to U2(l)
through voltage divider R12-R13, drives U2(l) to the
same voltage as U2(2); +2.5 Volts. So the output must be
+5 Volts because R12 and R13 are almost equal.
The U2 regulator oscillates at about 25 kHz. This signal,
which is set by R7 and C4, switches Q2-Q1 on and off.
When Ql is on, current is forced through LI because CRl
is reverse-biased. When Ql switches off, the polarity of
LI reverses to keep current from flowing from ground,
through CRl and LI, and to the load. The output voltage
is regulated by U2 adjusting the time t h a t Q1 is switched
on for every cycle. In normal operation, the duty cycle is
about 35 percent. A soft start is provided by C6, R l 1 and
CR3. C5 and R10 provide compensation for the internal
U2 operational amplifiers.
Short-circuit protection is provided by U l . During
normal operation, the voltage at Ul(2) is greater than
the voltage at Ul(3) (about +5.08 Volts and +4.95 Volts).
Therefore the output of U l is low. When the load current
\ through R l is greater t h a n 950 milliamperes, the voltage
at Ul(2) is less than the voltage at Ul(3). The output of
U l goes up to about +3 Volts and switches U2 off
through R14. U l will keep U2 switched off while the
:
short-circuit condition continues.
; A5A3 10 MHz-to-1 P P S Divider and Delay
: The A5A3 board generates a one pulse-per-second signal
I that provides the front-panel 1 P P S output. The 1 PPS is
]
synchronized to a n external signal from the rear-panel
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