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Model 5065A
Circuit Diagrams, Theory, and Maintenance
DIGITAL DIVIDER A5 THEORY
GENERAL DESCRIPTION
In instruments equipped with Time Standard Option
001 or 003, digital divider circuits provide 1 PPS for
A16 Assembly (also part of Time Standard Option) which
in turn provides two outputs:
(1) 1PPS"tick" pulses at
the front-panel 1 PPs jack and, (2) the push-pull clock
drive for the front panel mechanical clock. Input to A5
module is the internally connected 1 MHz signal from
the Frequency Dividers. The top cover is removed for
access to A5 controls and the mechanical clock adjust
ment. Time Standard Option 001 controls are as follows:
a. The TIME DELAY thumbwheel switch on A5
module. This control has six thumbwheels for 1 ,usec
to 1 sec incremental delay of the output "tick" pulse.
b. The TIME DELAY 0-1 iisec screwdriver adjust
ment on A5 module provides continuous delay control
over any 1 jusec portion of the TIME DELAY thumb
wheel switch setting.
c. The FAST and STOP pushbuttons on A5 module
permit setting the mechanical clock to the nearest
second.
d. The SYNC pushbutton on A5 module is used
for automatic synchronization of the output 1 PPS
"tick" pulse within 9 to 11 usec of an external reference
sync pulse. This sync pulse must be greater than +5 V
with a rise time of less than 0.05 psec.
e. The "set" knob at the rear of the mechanical
clock provides for minute and hour adjustment.
Five subassemblies make up the overall assembly:
a. A5A1 Adapter Board
b. A5A2 Master Clock Board
c.
A5A3 Preset Clock Board
d.
A5A4 Switch Circuit Board
e. A5A5 Interconnect Board
NOTE
In the following paragraphs, add"A5" to
the reference designations used for a com
plete reference designation.
Example:
A3IC3 = A5A3IC3.
The 1 PPS "tick" clock pulse and 1 PPS clock-drive
output are generated by:
(1) digital division and,
(2) both incremental and continuous delay. This tech
nique, illustrated by the A5 Block Diagram provides
for 0 to 1 sec delay of the 1 PPS "tick" output.
1 MHz from a buffer amplifier in the A4 module con
nects to the master clock. This master clock section is
a10
6
decade counter which produces 1 PPS pulses. The
1 PPS pulses activate the preset clock which delivers
a digitally delayed 1 PPS pulse. The preset clock pro
vides for delay in increments of 1 /usec up to 1-second.
The TIME DELAY thumbwheel switches provide the
preset delay information.
Continuously variable delay
over a zero to 1 /isec period is furnished by the zero to
1 jusec TIME DELAY control working in conjunction with
an adjustable one-shot multivibrator.
The variable
delay adds to the incremental delay to provide fully
adjustable delay from zero to one full second.
With the reset gate open, 1 MHz pulses are processed
in the input filter shaper and applied through the feset
gate to 1 MHz MV A2IC2 as shown in the Functional
Block Diagram. This IC drives master preset clock MV
A2IC3 and also delivers a 0.2 /usec pulse to output gates
A3IC2 and A3IC12B.
A2IC3 feeds 0.2
jusec, 1 MHz
pulses to the master clock and the preset clock as count
pulse inputs.
The master clock consists of six, serially-connected,
divide-by-10 decades for a 10
6
division, thus producing
the 1 PPS output. These 100 msec, 1 PPS output pulses
initiate reset and preset of the preset clock.
When
actuated by a master clock pulse, reset one-shot mV .
A3IC15 delivers a 1.3
^sec reset pulse to the preset
clock, and also triggers preset one-shot mV A3IC16.
This IC delivers a 0.5 ;usec preset pulse to the thumb
wheel switch circuits to preset thumbwheel binary in- -
formation into the preset clock and thus produce the
required delay. A coincidence output from NOR gate
A3IC17B holds the preset clock input closed during the
reset and preset period.
At the end of the reset and preset period, 1 MHz pulses
from A2IC3 drive the preset clock until the total of
preset counts plus the number of 1 MHz pulses = a
999,999 count.
At this time, the 9's detector circuit
provides the necessary inputs to AND gate A3IC12A for
a 1 fisec, 1 PPS output. This is the gating signal for -
A3IC2C.
This 1 PPS output is incrementally delayed by the
thumbwheel switch setting. The second input to AND -
gate A3IC2C is the train of 1 MHz pulses from A2IC2.
Coincidence between A3IC2C inputs produces a 0.2^sec
output that connects through NOR gate A3IC2D to the
variable delay circuit on A5A4 circuit board and to t h e
-
clock drive amplifiers.
Variable delay from 0 to 1 jusec is furnished by the TIME
DELAY screwdriver control to adjust variable one-shot -
mV A4IC1.
The amplified A4Q1 output connects
through J3 to A16 module where the 1 ((S pulse is
shaped and narrowed for the "tick" output at the front
panel 1 PPS jack.
The other output of A3IC2D is amplified by Q13 and
Q15 for an output to the clock drive circuit in A16_
module. To speed up the clock drive output, the FAST
pushbutton is depressed for a 10-PPS output. To slow
down the clock, the STOP pushbutton
shorts the
clock output to ground when depressed.
_
8-28
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