HP 5065A Operating And Service Manual page 150

Model 5065A
Circuit Diagrams, Theory, and Maintenance
2. Unregulated +12 Vdc from the 5065A used ex­
clusively to operate the CMOS circuits in the
clock.
3. 1 PPS signal from the 5065A used to synchronize
the clock and increment the display.
4. AC line sense signal from A2(9) turns off the dis­
play portion if instrument AC power fails or is
removed. To display time, when AC power is not
available, the clock front-panel STANDBY READ
must be pressed.
5. 1 PPS and 12 Vdc common.Circuit ground con­
nects to the chassis through the LED digital
clock circuits.
Three circuit boards make up the A19 LED digital clock.
These are:
1. A1, +5V switching regulator. This is the rear
board.
2. A2, 50 Hz logic. This is the middle board.
3. A3, clock display. This is the front board.
A1, +5V Switching Regulator
This assembly is a 9 kHz to 18 kHz switching regulator
which generates +5V, ±4 Vdc from the instruments' un­
regulated +28 Vdc input. It consists of switch Q1, voltage
regulator U1, current limit circuit Q2 and input and out­
put filter circuits.
The +28 Vdc input voltage is filtered by C1, L1, C2 and
is applied to U1 (8) and Q1. U1 (7) output is a +5 Vdc rec­
tangular wave signal which switches Q1 at a 9 to 18 kHz
rate depending on load current and input voltage.
A reference voltage output is generated at U1(4) and is
applied to U1 (3). The filtered +5 Vdc output is monitored
at U1(2) and any differences between U1(3) and U1(2)
changes the duty-cycle of U1(7) output. The duty-cycle
change adjusts Q1 on-off Times. If the +5 Vdc output
tends to increase, Q1 on-time decreases which reduces
the output voltage. If the +5 Vdc output tends to de­
crease, Q1 on-time increases which increases the output
voltage.
Current limiter Q1 senses the current flow through R8.
Excessive current turns Q1 on and is sensed at U1(9).
This sets U1 into current-limit mode which reduces the
+5 Vdc output to zero. Current limit occurs at about
450 mA. When the cause of excessive current is removed,
the +5 Vdc output returns to normal.
Diode CR1 is a commutating diode which conducts L2
coil current during Q1 off-times. R1, CR8 are part of an
ac sense circuit which monitors the unregulated, instru­
ment generated dc and switches the clock display off
whenever ac power is not available.
A2, 50 Hz Logic Board
The 50 Hz logic board generates the 50 Hz signal which
operates the clock display. It also synchronizes the clock
display advance with the instrument generated 1 PPS —
signal. This board also contains the ac sense circuits
which turn off the clock display whenever ac power to
the instrument is not available.
When power is first applied, the RC time constant of R3,
C1 causes one shot M.V. U3B(13) to generate a pulse
output. The pulse period is determined by the RC time —
constant of (R7-C3). U3B(13) output resets U3A which
sets U3A(1) low and disables gate U1B. With this gate
disabled, no clock pulses are gated thru U1B to U2(1). _
U3B(13) one-shot output is also gated thru U5B, clocks
U6B and turns on the 65 Hz free running M.V. comprised
of U1D, U5D and its associated components. The 65 Hz " ~ ~
output from U5D is gated thru U5A to the A3 clock dis­
play board U1(19). U1, on A3 clock display board, ac­
cumulates the 65 Hz pulses and generates a pulse output _
at 50th pulse (1 second). This pulse is used to synchro­
nize the clock display with the instruments' 1 PPS. The
1-second clocks U3A on A2, 50 Hz logic board. U3A(1)
output goes high, enables U1B and allows the 65 Hz
pulses to clock U2. U2 counts to 49 which is sensed by
U4C. U4C output is inverted by U4A, gated thru U4B and
inverted again to a high level thru U5C. This level resets —
U6B and turns off free-running M.V. U1D U5D.
Accumulator U1 on A3 clock display board, has counted _
to 49. The instrument 1 PPS input to the 50 Hz logic
board is "stretched" and level-changed thru Q2 and
clocks U6A. U6A is a one-shot M.V. whose 75 usec period
is determined by R6, C2 RC time-constant. U6A(1) out- ~ ~
put is gated thru U5A to A3 clock display board U1, as
the 50th cycle. The clock display then advances one
second. The U6A output pulse is delayed by R8-C4, —
gated thru U5B(5) and clocks U6B which starts free-
running M.V. U1D, U5D.
The delay circuit R8, C4 provides a time delay between
the 1 PPS generated 50th cycle, which causes the display
to increment 1 second, and the start of the next free run­
ning M.V. cycle, which enables U1 on A3 clock display
board to count to 49.
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