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Model 5065A
Circuit Diagrams, Theory, and Maintenance
THE PRESET DIVIDER
The preset divider is made up of four decades giving a
total dividing capability of 10,000.
With each 10,000
counts applied to the divider input, there will be one
output pulse. With the addition of the preset capability
this divider can be set to divide by any integer (except
1 through 12, due to reset and preset time). Since the
divider can be set to divide by any predetermined
integer, the system is considered a divide-by-n preset
divider. For example: if the divider were to divide-by-
2, and 8 would be preset into the decade before the
counting sequence starts, and since an 8 count is already
in the decade from the preset, it will take only 2 inputs
to get 1 output. Conversely, to divide-by-8, 2 counts are
preset into the decade prior to counting.
The preset divider delivers an " H " output to the sample
circuit at the 9988 count (the sume of the input 5 MHz
pulses and the preset information of the four decades).
Output stage IC5 remains "on" with an " H " output
during count 9989. Count 9990 turns off IC5 and starts
a 1.5 jusec reset period. Inhibit gate Q1 and Q2 closes to
prevent 5 MHz pulses from entering the decades during
the reset and preset peiod. During reset, the decades
are restored to "0" count. Following the reset period is
a 0.5 jusec preset period. At this time, the thumbwheel
switch preset information is fed to the four decades.
At the end of the preset period, inhibit gate Q1 and Q2
opens and counting resumes. The counting cycle re
occurs at the 5 MHz/n rate determined by the thumb
wheel setting.
The 5 MHz input signal is shaped by the negative-
clamping action of Q1, the first half of inhibit gate Q1
and Q2. The 5 MHz pulse is then applied to first de
cade IC2(5) which responds to the positive-going tran
sition of the input pulse. The four decades are series con
nected through inverting amplifiers in IC1, IC3, and IC6,
and also through inverting amplifiers Q4 and Q9 as shown
in the Synthesizer Timing Diagram on page 7-16. Each
decade responds to the positive-going transition of the
input pulse at pin 5. Connecting to the " 1 " , "2", "4", and
"8" inputs of each decade are the thumbwheel-switch
connections through which the decades are preset as
required for the desired Synthesizer frequency as derived
from Table 3-9. The thumbwheel switch puts in binary
information for the desired preset count as can be seen by
the wiring diagram for one thumbwheel-switch section
shown below. The decade count will therefore be thetotal
of the preset information plus the number of input 5 MHz
pulses.
When the count reaches 9000 (preset information plus
the number of 5 MHz pulses), final decade IC10 delivers
an "8" pulse from IC10(1) to IC9(3) and a " 1 " pulse
from IC10(6) to IC9)5). These inputs activate a NOR
Table 3-9. Typical Thumbwheel Switch Section
gate which delivers a coincidence "9" output (H) pulse
at IC9(6). This " H " pulse is inverted by Q11 for the
first " 1 " input to IC5(1).
When the count reaches 9900, third decade IG7 delivers
an "8" pulse from IC7(1) to IC6(5) and a " 1 " pulse from
IC7(6) to IC6(3). These items activate a NOR gate in
IC6 which delivers a coincidence "9" output (H) at
IC6(6), which is then inverted by Q8 for the second
"L" input to IC5(2).
When the count reaches 9980, second decade IC4 de
livers an "8" pulse from IC4(1) through an inverting
amplifier in IC3 (IC3-5 to IC3-6) to Q6. Q6 inverts this
pulse for the third "L" pulse at IC5(3).
When the count reaches 9988, first decade IC2 delivers
an "8" pulse from IC2(1) to IC5(5) for the final "L" pulse
which activates IC5.
Since IC2 output remains un
changed during count 9989, IC5 remains activated until
count 9990. At this count, IC2(1) output goes " H " and
turns off NOR gate IC5. Thus, IC5 output pulse is two
input counts wide or 0.4^sec.
Reset one-shot multivibrator IC11 is triggered when
NOR gate IC5 closes and provides a 1.5 jusec pulse to
Q16, Q7, and preset one-shot multivibrator
IC8(9).
The signal through Q16 is amplified, inverted, sent to
NOR gate (Q13, Q14) and then applied to amplifier Q3.
When Q3 collector goes "H", the input gate closes for
the 1.5 jusec reset period. The reset signal through Q7
is amplified, inverted, and applied to decade IC4(2).
Decade IC2 count is "0" but IC4, IC7, and IC10 are at
the count of "999". The reset pulse into IC4(2) cycles
7-15
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