Table of Contents
Advertisement
SYNC I N P U T connector. The 10 MHz from A5A1 is
applied to all of the decade counters, U8 through U14.
ENABLE P and ENABLE T (Pins 7 and 10) of U l l are
always enabled (always held high). Therefore, every
time the clock pulse occurs, that counter changes state.
The least significant bit in this counter chain is pin 14 of
U l l . If this point is monitored with an oscilloscope, a 5
MHz signal is displayed. U l l pin 13hasa"2MHzsignal,
and pin 11 has a 1 MHz signal. Pin 15, the ripple-carry
output of U l l , also has 1 MHz. TheUll(15) outputisnot
a square wave. It is approximately a 100-nanosecond
pulse that occurs every microsecond. During the one
clock period t h a t Ull(15) is held high, pins U14(10 and
7) are enabled, and U14 is clocked one time. Then the
ripple-carry output of U11 goes low again disabling U14.
Later clock pulses do not change U14 until the ripple-
carry output of U l l once again goes high ten cycles
later. This occurs all the way up the chain to U8, which
has the most significant bits, and U8(ll) is actually
pulsing at a 1 Hz rate. The signal from U8(ll) is used to
generate the non-delayed 1 PPS. This signal is not used
in A5; it is used only for factory testing.
TIME DELAY Switches and Dividers Operation
The A5A3 Digital Divider has seven thumbwheel
switches t h a t allow the delay to be set in 100-second
steps. When all thumbwheels are set to zero, the delay
between the reference pulse and the delayed pulse is 100
nanoseconds plus or minus 100 nanoseconds. An
example of how this circuit works is demonstrated by
looking at switch SI which is compared to the outputs of
U l l . I f S l ( 1 0 ) i s l o w a n d S l ( l l ) h i g h , p i n 7 1 o w , a n d p i n 2
high, then when Ull(14) goes high while Sl(10) is low,
these two outputs have different states and the output
U7(3) goes high (U7 is an exclusive OR gate). In the
same way, if all of the outputs of U8-U14 were opposite to
what they are being compared to, then all outputs of the
exclusive OR gates would go high simultaneously. T h a t
is, if Ull(14) were iri the complementary state of S l ( l l ) ,
and t h a t condition was the same all the way through
this set of exclusive OR gates (U1-U7), there would not
be any open collector outputs t h a t are pulled low and so a
pulse would be sent to U18B. This happens once every
second when the output state of U8-U14 is exactly the
opposite in the absolute sense of the switch settings.
This generates the delay t h a t the operator desires.
A5A4 Interconnect
The A5A4 Interconnect Board provides electrical con
nections between the A5A1, A5A2, and A5A3 sub-
assemblies of the A5 Digital Divider. There are no active
circuits on A5A4.
A5 DIGITAL DIVIDER MAINTENANCE
The A5 Digital Divider provides one pulse-per-second
output signals a t the H P 5065A front panel, and to the
front-panel digital clock. A 1 MHz signal from the A4
100 kHz Frequency Divider is the input signal to A5.
A5 Preparation for Troubleshooting and Adjustments
Model 5065A
Circuit Diagrams, Theory, and Maintenance
The A5 Digital Divider can be removed from the chassis
for servicing. The extender board supplied with the HP
5065A (HP Part Number 05061-6073) can make circuit
parts accessible for testing. Use the following procedure
to remove A5 from the chassis for troubleshooting and
adjustment:
NOTE
A5 can be removed from the chassis with the power
still applied to the HP 5065A. Be careful of the high-
voltage terminals inside the 5065A cabinet. Extender
board (HP Part Number 05061-6073 In accessory kit)
makes A5 components accessible.
a.
Remove the cabinet top and bottom covers.
b. Disconnect the three coaxial connectors ( J l , J2,
and J3) from the A5 module at the bottom of the
chassis. Disconnect the four single wires (B, R, W,
and R) from the A5 module at the bottom of the
chassis.
c. Remove the screws that hold the A5 module in the
chassis, and carefully remove the A5 from the
chassis.
d.
Remove the screws that hold the A5 module shield
cover, and remove the cover.
e. Reconnect cables and wires to supply power signal
connections to A5.
f.
Keep the A5 assembly in a position such t h a t no
electrical connections are short-circuited.
g. After repairs and adjustments are complete, re
place the A5 Divider in its normal position in the
5065A chassis.
A5 Adjustments (Tuning)
Use the following procedure to check and adjust the A5
Divider after repair or replacement with a new unit:
a.
With the A5 Divider out of the chassis a n d set up
for maintenance, connect the vertical input of an
oscilloscope to the junction of A5A1L1 and
A5A1Q3. The oscilloscope display should be a 10-
MHz sine wave signal with ten cycles t h a t decay
from about 3 to 4 Volts peak-to-peak to some small
amplitude, and then the decaying waveform re
peats continuously.
b. Adjust LI with a nonmetallic tool for maximum
signal on the oscilloscope.
c. Connect the oscilloscope to the junction of A5A1L3
and A5A1Q5. The oscilloscope display should be a
10-MHz sine wave signal at about 5 to 6 Volts peak-
to-peak.
d. Adjust L3 with a nonmetallic tool for a maximum
signal on the oscilloscope. Then adjust LI again
for maximum signal at L3-Q5 junction.
(SERIES 2 3 4 0 )
8 - 2 9
Advertisement
Table of Contents
