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Model 5065A
Circuit Diagrams, Theory, and Maintenance
DIGITAL DIVIDER POWER SUPPLY A16 THEORY
The A16 module has three basic circuits:
a.
Inverter
and
regulated
power
supply
that
supplies a +4.2 V output, and a +13.3 V zener-stabilized
and filtered output for use in A16 circuits.
b.
Blocking oscillator and output amplifier that
supplies the 1 PPS tick pulse to the 1 PPS output jack.
c. The clock movement amplifier that supplies a
push-pull square wave output to energize the clock.
The saturable-transformer, inverter oscillator of Q1,
Q2, and T1 is powered by +20 V that is filtered by L1
and C1. R1, C2, and CR1 are a start circuit.
R2, R3,
C4, and C5 provide fast response, but limit average base
current to improve inverter efficiency.
Inverter fre
quency is about 1 kHz.
Inverter output to the +4.2 V
regulator is +6.5 V, full-wave rectified by CR2 and CR3,
and filtered by C6.
In the regulator circuit, differential amplifier Q4 and
Q6 compares a reference voltage developed by voltage
divider R5 and R6 with the feedback dc voltage at the
movable tap of +4.2 V control R13.
Thus, the dif
ferential amplifier derives an error voltage. This error
output at Q4 collector controls Q5 through Q3 to hold
the regulated output at +4.2 V. Bypass elements R7 and
C10 at Q5 base prevent oscillations.
Further filtering
for large load surges is provided by C17 and C18, with
C17 providing high frequency filtering.
The second output of T1 energizes full-wave bridge
rectifier CR4, 5, 6, and 7 to supply a positive dc output
which is filtered by C7 and zener-stabilized at +13.3 V
by CR8.
Several elements of RC and LC filtering
provided circuit decoupling.
Input 1 PPS pulses to the output tick blocking oscillator
couple through J2 from A5 Digital Clock. Diode CR15
at Q7 base blocks any negative component of the input
pulse. Q7 drives blocking oscillator transformer T2 and
feedback to Q8 provides the regenerative action.
8-66
Diode CR9 protects Q7 and Q8 collector junctions. In
T1 output, CR1 provides isolation.
Selectable resistor
R15 determines the output pulse width.
Output tick
pulses are provided by emitter followers Q9 and Q10.
s
-
Zener diodes CR11 and CR12 limit output pulses to 10
volts peak. Q10 output is not used. Q9 output feeds the
_
1 PPS output jack.
1 PPS drive pulses connect from A5 Digital Divider
through J1 to IC1 of the clock movement amplifier. IC1
—
provides flip-flop action and furnishes a push-pull out
put to clock amplifiers Q11 andQ12. The push-pull out
put of power amplifiers Q11 and A12 connects to the
front panel clock and is limited to 10 V peak by zener
—
diodes CR13 and CR14.
A16 MAINTENANCE
NORMAL OPERATION
The one-shot multivibrator output from A5A4, provides
triggering for the Blocking Oscillator.
This output is
amplified and appears at J3 and a 1 PPS, 20 yus, +10 V
pulse.
The power inverter provides +4.2 Vdc and +13.3 Vdc
for A5 integrated circuits.
Transistors Q1 and Q2
produce a 2 kHz pulse through T1 to the power supplies.
The output of A3Q15 is applied to clock movement flip-
flop IC1. This flip-flop drives amplifier Q11 and Q12
which drives the clock movement.
OPERATIONAL CHECK
With unit power on, check with a dc voltmeter, for +4.2
V + .1 V across C17. Check for a +10 V, 20 yusec pulse at
A16J3.
TROUBLESHOOTING
-
Digital divider power supply common is isolated from
instrument common. To observe waveforms and meas
ure divider voltages, divider common may be connected
to instrument common for troubleshooting with no
adverse effects.
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