Avoiding Address Generation Pipeline Interlocks; Stack Extension Delays - Motorola DSP56600 Manual

Pipeline Interlocks

Stack Extension Delays

6-8 Optimizing DSP56300/DSP56600 Applications
instruction and no interlock cycles will be added to the execution of
the second MPY instruction:
move
move
move
mpy
mpy
6.2.2 Avoiding Address Generation Pipeline
Interlocks
There are few common ways to avoid the Address Generation
pipeline Interlock. The first is to change the order to the instructions
such that a sequence that caused the interlocks will not be part of
the re-ordered code. The second is to put some useful instructions
inside the sequence such that the new sequence of instructions will
not generate interlock cycles.
An example of code reordering is described in the following
example:
move
move
move
move
move
In the above example, 3 address generation pipeline interlock cycles
are added to the execution of the last instruction. By reordering the
instructions in that code however, the interlock cycles are avoided
completely:
move
move
move
move
move
6.3 STACK EXTENSION DELAYS
Some instructions access the System Stack as part of their normal
activity. If the stack is full or empty, execution of instructions is
halted, and a stack extension on-chip hardware (if enabled) is
engaged. The stack extension hardware will move stack words from
the hardware stack to data memory or from data memory to the
#addr,R0 ;R0 is destination
#data,X0
#data,Y0
X0,Y0,A X:(R0)+,Y0;Instruction uses R0
X0,Y0,A X:(R0)+,Y0;Instruction uses R0
#1,r1
#3,r2
#<$50,y0
#table,r0
x:(r0),x0
#table,r0
#1,r1
#3,r2
#<$50,y0
x:(r0),x0
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