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In the following example, the DMA receives data from the ESSI and
passes it to a memory buffer. Only after the buffer is filled the DMA
interrupts the core. Each ESSI request triggers a transfer of one
word. After N words are transferred, the DMA is disarmed and
interrupts the core. The core re-arms the DMA at the end of the
interrupt routine.
;================= initialize DMA
movep
movep
movep
;DMA control word:% 0 1 101 11 0 01010 0 101 100 00 00
;
DE
0
;
DIE
1
;
DTM
101
;
;
DPR
11
;
DCON
0
;
DRS
01010
;
D3D
0
;
DAM[5:3]101
;
DAM[2:0]100
;
DS[3:2] 00
;
DS[1:0] 00
movep
;============== initialize ESSI0
movep
movep
movep
;============== initialize the core
bset
ori
...
;============== interrupt vector area
org
jsr
...
;============== subroutine area
_ESSI0_RX
jsr
movep
bset
rts
MOTOROLA
Optimizing DSP56300/DSP56600 Applications
#M_RX0,x:M_DSR0;address of ESSI receive
;register is transfer source
;address.
#DATA_BUF,x:M_DDR0;base address of memory data
;buffer is transfer dest.
#BUF_SIZE-1,x:M_DCO0;load number of transfers
;before core is interrupted.
channel not armed (yet)
DMA interrupts enabled
word transfer triggered by request source
DE is not disarmed at end of word trans.
highest channel priority
continuous mode disabled
DMA request source - ESSI0 receive data
3 dimensional mode disabled
destination address post-increment
source address no update
transfer destination: x memory.
transfer source: x memory.
#$6e52c0,x:M_DCR0;load control register.
#$3f,x:M_PCRC
;enable all ESSI0 pins
#$180000,x:M_CRA0;24 bits per word, maximal
;frequency
#$011130,x:M_CRB0;transmitter enabled, one bit
;sync (sc2 output) syn mode,
;internal clocks.
#13,x:M_IPRP
;give DMA channel 0 interrupt
;priority 1.
#$3,mr
;enable interrupts
p:I_DMA0
<_ESSI0_RX
<_PROCESS_DATA
#DATA_BUF,x:M_DDR0;reset destination register at
;beginning of memory buffer.
#23,x:M_DCR0
;re-arm channel 0
Using the DMA
Servicing a Peripheral
4-7
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