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In addition to the latch-off enable function, this pin is also built for the selection of burst mode enable or
not during configuration before softstart. If the burst mode is enabled, the gate drives will be disabled if
LOAD pin voltage falls below 0.12V. However, if burst mode is not selected, the gate drives will not be
stopped by LOAD pin voltage.
The selection block works only after the first time IC VCC increases above UVLO. After CVCC is higher
than turn on threshod, a current source
. After 26μs, IC will compare the voltage on EnA pin and 1.0V, if voltage on EnA pin is higher than
C
EnA
1.0V, the burst mode function will be enabled. As the voltage on EnA pin depends on
selecting different capacitance value, whether this IC works with burst mode can be decided.
= M
Ω
1
With
and
R
EnA
=
*
1 (
V
I
R
EnA
sele
EnA
Therefire burst mode will be enabled. If
mode will be disabled.
After the selection is done, the current source
IC starts to sense the EnA pin voltage latch off enable purpose. This blanking time is used to let the EnA
pin votlage be stablized to avoid mistriggering of Latch-off Enable function.
2.4
Design of Synchronous Rectification (SR) control
Synchronous Rectification (SR) in a half-bridge LLC resonant converter is one of the key factor to achieve
high efficiency. SR control is a major benefit we offer with our new LLC controller IC ICE2HS01G.
Before going into details of SR control of the IC, it's necessary to understand the ideal SR switching
mechanism for two typical working conditions, i.e. when operation frequency(
and above the resonant frequency (
gate),
(primary low side gate),
V
LG
(current flowing through secondary high side MOSFET),
I
SH
side MOSFET) and
I
PRI
Application Note
, in addition to the
I
sele
=
1
, the voltage at EnA pin at the time of 26us can be calculated as:
C
nF
EnA
−
6
26
*
10
−
−
=
)
100
*
10
e
RC
C
EnA
>
).Figure 7 illustrates the waveforms of
f
f
sw
r
( secondary high side gate),
V
SHG
(current flowing through primary resonant tank).
, is turned on to charge the capacitor
I
EnA
26
*
10
−
−
−
6
6
6
*
10
*
1 (
10
*
10
e
V
is set to be 10n F,
EnA
is turned off. A blanking time of 320μs is given before
I
sele
( current flowing through secondary low
I
SL
16
and
R
EnA
−
6
−
=
>
9
)
. 2
56
1
0 .
V
V
=
<
. 0
26
1
0 .
@
26
V
V
us
) is below (
f
sw
(primary high side
V
HG
(secondary low side gate),
V
SLG
, by
C
EnA
thus burst
<
)
f
f
sw
r
2011-07-06
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