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From Figure 9 below,
R
should start with a smaller SR on time for safety and then adjust it to achieve higher efficiency.
Figure 9
SR on time versus SRD resistance
A simple constant on time control does not provide the best efficiency of LLC HB converter for the whole
load range. In fact, the actual resonant period of secondary current reduces when the output load
decreases or input voltage increases. The primary winding current can reflects this change. The current
sense circuit can be designed to get such information and input to CS pin. In ICE2HS01G, a function
called current level (CL) pin is implemented. During heavy load and low input voltage, the CL pin voltage
)
(
is clamped at same voltage of SRD pin, 2V. Therefore, the SR on time in such conditions is
V
CL
determined by
only and is equal to
R
SRD
is reduced to be lower than 2V and extra current will be drawn from SRD pin, thereby the actual SR
V
CL
on time is reduced. The relationship between
can be adjusted to find the suitable reducing speed of SR on time for either better reliability or better
efficiency.
is normally around 10 times
R
CL
calculation for the 300W design example:
We obtain the
for full load condition, based on the circuit in Figure 5:
V
CS
2
*
R
I
=
2
_
_
max
cs
in
rms
V
π
cs
The corresponding
V
CL
Then for
= 0.4V where
V
CS
around 16A output current(Figure 10, bottom).
Application Note
is selected to be 66kΩ to achieve
SRD
T
_
max
on
V
R
SRD
2
*
68
*
. 2
06
C
=
1
*
cs
π
C
r
is clamped at 2V according to Figure 10(top) and the SR on time is
is exactly 2V, the corresponding load is 63% of the full load, which is
V
CL
T
_
max
on
. In case of light load, with low CS voltage(
and
is shown in Figure 10(top). The resistor
V
CS
CL
, which is 680kΩ in this design. Below is the detailed
−
12
470
*
10
=
*
. 0
635
V
−
9
66
*
10
19
=
. 5
31
. Usually customer
us
V
CS
T
on
), the
R
CL
.
_
max
2011-07-06
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