Miller Clamp Activation Or Deactivation; Gate_Sense Pin; Example Propagation Delay Testing - Analog Devices EVAL-ADuM4138EBZ User Manual

UG-1194
Temperature Sense Fault Override
Without remote temperature sensing resistors in place, the TS1
and TS2 pins float high, which produces a low temperature
operation mode. To create a middle range voltage on the tempe-
rature sense pins, place an approximately 1.8 kΩ resistor on R23
or R24. These resistors can be removed by jumping P12 and P13
to different pin configurations, or the TS1 and TS2 pins can be
fed by a voltage source. Jumper P11 and Jumper P12 are provided
to allow the user to quickly tie Pin TS1 or Pin TS2 high or low,
effectively railing these pins to make the
the temperature sensor is experiencing a low or high temperature.
A third option is to connect to the 1.8 kΩ resistors to obtain a
midrange temperature simulation, as shown in Figure 6.
Figure 4. TS1 and TS2 Pins Jumped High (Low Temperature Simulation)
Figure 5. TS1 and TS2 Pins Jumped Low (High Temperature Simulation)
Figure 6. Midrange Temperature Sense Jumper Configuration
ADuM4138 sense that
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EVAL-ADuM4138EBZ

MILLER CLAMP ACTIVATION OR DEACTIVATION

In the stock configuration, P2 is jumpered. In this configuration,
the Miller clamp is able to be operated. Removing the P2
jumper removes the pull-up resistor from the gate of the
external Miller clamp metal-oxide semiconductor field effect
transistor (MOSFET), which sends a low signal to the Miller
clamp constantly, because the MILLER_OUT pin is open-drain.

GATE_SENSE PIN

The P1 jumper allows access to connect and disconnect the
GATE_SENSE pin for manipulation testing. The left side of this
pin is connected directly to the IC and the right side is
connected to the available sensing node of an IGBT module. It
is recommended always to leave the P1 jumper connected,
unless a specific test is required, for example, testing the Miller
clamp activation voltage.

EXAMPLE PROPAGATION DELAY TESTING

From a stock configuration, an example propagation delay
testing can be performed. Figure 7 shows one possible
configuration. The VI+ pin is driven via a 5 V push-pull CMOS
driver referenced to GND . Pin V
1
to GND . The E screw terminal is the emitter connection of the
1
secondary side, which is also the GND
it is recommended to remove the USB-SDP-CABLEZ, as well as
the P18, P19, P20, and P21 jumpers. If an SPI transmission
occurs when the VI+ pin is brought high, the output is blocked.
It is possible to perform a test with the
connected to the ADuM4138.
Measuring Test Point TP7 and/or Test Point TP23 simulates
what an IGBT with a 1 Ω internal series gate resistance sees at
its gate.
Adding or removing the P2 jumper affects the rising edge
propagation delay, because the
safe to turn on the main V
OUT_ON
MOSFET gate voltage. Do not allow the VI+ pin to be driven by
a high-Z signal, which can happen on some function generator
models when the output off button is pressed. If the function
generator being used has a high-Z when turned off, it is
recommended to leave P26 jumpered by placing a 50 Ω
terminating resistor, R8, between VI+ and GND
Figure 7. Example Propagation Delay Test Setup
User Guide
is fed with 12 V referenced
DD1
pin. For this configuration,
2
USB-SDP-CABLEZ
ADuM4138 senses when it is
driver, based on the Miller
.
1