Signal Trace Geometry - Intel 82541PI Design Manual

•
The reference plane for the differential pairs should be continuous and low impedance. It is
recommended that the reference plane be ground (or 1.8 V, the voltage used by the 82541PI
PHY). This provides an adequate return path for high frequency noise currents.
•
Do not route differential pairs over splits in the associated reference plane.
•
Differential termination components should be placed as close as possible to the LAN
controller.
4.4.1

Signal Trace Geometry

The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width
to trace-height above the ground plane. To minimize trace inductance, high-speed signals and
signal layers that are close to a ground or power plane should be as short and wide as practical.
Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1. To maintain
trace impedance, the width of the trace should be modified when changing from one board layer to
another if the two layers are not equidistant from the power or ground plane.
Each pair of signals should have a differential impedance of 100 Ω. +/- 20%. If a particular tool
cannot correctly calculate or predict differential traces, it is permissible to specify 55 to 60 Ω
single-ended traces as long as the spacing between the two traces is minimized. As an example,
consider a differential trace pair on Layer 1 that is 8 mils (0.2 mm) wide and 2 mils (0.05 mm)
thick, with a spacing of eight mils (0.2mm). If the fiberglass layer is 8 mils (0.2 mm) thick with a
dielectric constant, E
calculated differential impedance would be approximately 100 Ω..
When performing a board layout, do not allow the CAD tool auto-router to route the differential
pairs without intervention. In most cases, the differential pairs will have to be routed manually.
Components should be laid out in the following order of priority:
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Differential traces
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Termination resistors
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Bypass capacitors
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Other components
Note: Measured differential trace impedance for layout designs targeting 100 Ω often indicates lower
actual impedance. Designers should verify actual trace impedance and adjust the layout
accordingly. If the actual impedance is consistently low, a target of 105 – 110 Ω should compensate
for second order effects.
It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential
impedance by up to 10 Ω, when the traces within a pair are closer than 30 mils (edge to edge).
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long
and thin traces are more inductive and would reduce the intended effect of decoupling capacitors.
Also for similar reasons, traces to I/O signals and signal termination should be as short as possible.
Vias to the decoupling capacitors should be sufficiently large in diameter to decrease series
inductance. Additionally, the PLC should not be closer than one inch to the connector/magnetics/
edge of the board.
Application Note (AP-468)
82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
, of 4.7, the calculated single-ended impedance would be about 61 Ω and the
R
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