Intel 82541PI Design Manual page 62

82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
Table 18. Ball Number to Signal Mapping (Sheet 8 of 8)
82541ER
Ball
Pin
Ref
Name
P4 AD[6]
P5 AD[3]
P6 AD[2]
P7 EECS
P8 VSS
P9 FLSH_SO
P10 EEDI
P11 CTRL12
P12 VCC
P13 SDP[1]
P14 NC
54
82541PI 82562GZ(GX)
Pin Pin
Name Name
AD[6] NC
AD[3] NC
AD[2] NC
EECS NC
VSS VSS
FLSH_SO/ NC
LAN_
DISABLE#
EEDI NC
CTRL12 NC
3.3 V VCC
SDP[1] JRXD[0]
NC NC
Population Options
82541ER 82541PI
AD[6] AD[6]
AD[3] AD[3]
AD[2] AD[2]
EECS EECS
VSS VSS
LAN_EN LAN_EN
EEDI EEDI
Pwr Regulator Pwr Regulator
3.3 V 3.3 V
LCI LCI
NC NC
82562GZ(GX) Comments
No stuff
No stuff
No stuff
EECS
VSS VSSPL = VSS
LAN_EN Connect to LAN
Enable signal
EEDI If desired, this
can be shorted to
the ICH EEDI
because it is an
input in ICH in
reset.
No stuff Connect to PNP.
Don't' stuff PNP
on
82562GZ(GX).
3.3 V
LCI ICH expects this
signal to be high
or undriven.
NC
Application Note (AP-468)