82541Pi(Er) Oscillator Solution; 82541Pi Clock Oscillator Specifications - Intel 82541PI Design Manual

82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
Table 16. 82541PI Clock Oscillator Specifications
Symbol
f0
df0
Dc
tr
tf
σi
C1
VDD
Operating
temperature
CMOS output
levels
3.6.10

82541PI(ER) Oscillator Solution

There are two oscillator solutions for the 82541PI(ER): high voltage and low voltage.
3.6.10.1 High Voltage Solution (VDD = 3.3 V)
This solution involves capacitor C1, which forms a capacitor divider with C
This attenuates the input clock amplitude and adjusts the clock oscillator load capacitance.
V
V
This enables load clock oscillators of 15 pF to be used. If the value of C
be adjusted by tuning the input clock amplitude to approximately 1 V
then C1 is 10 pF ±10%.
A low capacitance, high impedance probe (C < 1 pF, R > 500 K Ω) should be used for testing.
Probing the parameters can affect the measurement of the clock amplitude and cause errors in the
adjustment. A test should also be done after the probe has been removed for circuit operation.
If jitter performance is poor, a lower jitter clock oscillator can be implemented.
22
Parameter
Frequency
Frequency Variation
Duty Cycle
Rise Time
Fall Time
Clock Jitter, rms (if specified)
Clock Capacitance (pushed by clock)
Supply Voltage
Voltage Output High (Voh),
Voltage Output Low (Vol)
= VDD * (C1/(C1 + C
in stray
= 3.3 * (C1/(C1 + C
in stray
VDD=3.3
C1~10pF
Clk oscillator
Board Capacitance
Not a Component
Min
-50
40
80% VDD
))
))
K14
X1
Cstray~20pF
Specifications
Typical Max
25 MHz
+30 ppm
60 %
5 ns
5 ns
50 ps
15 50 pF
3.3 or 1.8 V
70 ° C
V
20% VDD V
of about 20 pF.
stray
is unknown, C1 should
stray
. If C equals 20 pF,
ptp stray
Tabor
82541PI(ER)
Application Note (AP-468)
Units