Introduction; Scope; Terms - Intel 82541PI Design Manual

1.0

Introduction

82541PI(ER) Gigabit Ethernet controllers and 82562GZ(GX) Platform LAN Connect (PLC)
devices are all manufactured in a footprint-compatible 15 mm x 15 mm, 196-ball grid array
package. Many of the critical signal pin locations on the 82541PI(ER) are identical to signals on
the 82562GZ(GX) allowing designers to create a single design that accommodates these two parts.
Because the usage of some pins on the 82541PI(ER) differ from the usage on the 82562GZ(GX),
the two parts are not referred to as "pin compatible". The term "footprint compatible" refers to the
fact that the parts share the same package size, same number and pattern of pins, and layout of
signals that allow for the flexible, cost effective, multipurpose design. Therefore, it is easy to
populate a single board design with any of the two parts to maximize value while matching your
customers' performance needs.
1.1

Scope

This application note identifies the design differences between the 82541PI(ER) and the
82562GZ(GX). The table in
For other necessary design collateral, please refer to
1.2

Terms

AFE
BER
DFD
DUT
ICHx
LCI
BGA
PLC
USB
Application Note (AP-468)
82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
Section 5.0 lists the pinout assignments for each of the two parts.
Analog Front End.
Bit Error Rate.
Dual Footprint Design — a design that uses an 82562GZ/GX device
®
with an Intel 82541PI(ER) Gigabit Ethernet controller.
Device Under Test.
I/O Controller Hub (ICH) that supports the 82562GZ(GX) PLC interface
(x = 5, 6, or 7).
LAN Connect Interface.
Ball Grid Array.
Platform LAN Connect.
Universal Serial Bus
"Reference Documents" (Section 1.3).
1