Intel 82541PI Design Manual page 6

82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
3.5 Flash Interface ....................................................................................................... 15
3.6 Designing with 82541PI(ER) Gigabit Controllers ................................................... 15
3.6.1 82541PI(ER) Gigabit Controller LAN Disable Guidelines............................ 15
3.6.2 Power Supplies for 82541PI(ER) Gigabit Ethernet Controllers ................... 16
3.6.3 82541PI(ER) Controller Power Supply Filtering .......................................... 17
3.6.4 82541PI(ER) Controller Power Management and Wake Up ....................... 17
3.6.5 82541PI(ER) Controller Test Capability ...................................................... 18
3.6.6 Serial EEPROM for 82541PI(ER) Controller Implementations.................... 18
3.6.7 EEPROM Map Information.......................................................................... 19
3.6.8 Magnetics Modules for 82541PI(ER) Controller Applications ..................... 19
3.6.9 Oscillators for 82541PI Controllers.............................................................. 21
3.6.10 82541PI(ER) Oscillator Solution.................................................................. 22
4.0 General Layout Considerations for Ethernet Controllers .................. 25
4.1 Guidelines for Component Placement ................................................................... 25
4.1.1 Crystals ....................................................................................................... 26
4.1.2 Board Stackup Recommendations.............................................................. 26
4.2 Critical Dimensions for Discrete Magnetics Module and RJ-45 ............................. 27
4.2.1 Distance A: Magnetics to RJ45 (Priority 1).................................................. 27
4.2.2 Distance B: PHY to Magnetics (Priority 2)................................................... 28
4.2.3 Distance C: LAN Controller to Chipset (Priority 3) ...................................... 28
4.2.4 Distance D: The Overall
4.2.5 Distance E: Ethernet Controller to PCB Edge ............................................. 28
4.3 Critical Dimensions for an Integrated Magnetics Module....................................... 29
4.3.1 Distance A: The Overall Length of Differential Traces ................................ 29
4.3.2 Distance B: Ethernet Controller to Chipset.................................................. 29
4.3.3 Distance C: LAN Controller to PCB Edge ................................................... 29
4.4 Differential Pair Trace Routing ............................................................................... 29
4.4.1 Signal Trace Geometry ............................................................................... 31
4.4.2 Impedance Discontinuities .......................................................................... 32
4.4.3 Reducing Circuit Inductance ....................................................................... 32
4.4.4 Signal Isolation ............................................................................................ 32
4.4.5 Power and Ground Planes .......................................................................... 33
4.4.6 Traces for Decoupling Capacitors ............................................................... 33
4.4.7 Ground Planes Under a Discrete Magnetics Module .................................. 34
4.4.8 Non-Integrated Magnetics Modules/RJ-45 Connectors .............................. 36
4.4.9 82562GZ(GX) Layout
4.5 82562GZ(GX) Signal Terminations........................................................................ 38
4.5.1 Termination Plane ....................................................................................... 39
4.5.2 Termination Plane Capacitance .................................................................. 39
4.6 Light Emitting Diodes for Designs Based on 82562GZ(GX) PLC .......................... 39
4.7 82541PI(ER) Signal Terminations.......................................................................... 40
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Length of Differential Traces from LAN to RJ-45 (Priority 4)....................... 28
Guidelines (Routing LAN 3.3 V When Using a Copper Trace).................... 37
Application Note (AP-468)