82541Pi(Er) Controller Power Supply Filtering; 82541Pi(Er) Controller Power Management And Wake Up - Intel 82541PI Design Manual

The 82541PI(ER) controller has a LAN_PWR_GOOD input. Treat this signal as an external device
reset which works in conjunction with the internal power-on reset circuitry. In the situation where a
central power supply furnishes all the voltage sources, LAN_PWR_GOOD can be tied to the
POWER_GOOD output of the power supply. Designs that generate some of the voltages locally
can connect LAN_PWR_GOOD to a power monitor chip.
The power sources are all expected to ramp up during a brief power-up interval (approximately
20 ms) with LAN_PWR_GOOD de-asserted. The 82541PI(ER) controller must not be left in a
prolonged state where some, but not all, voltages are applied. The 3.3 V source should be powered
up prior to the 1.2 V or 1.8 V sources. The 1.2 V and 1.8 V power supplies may power up
simultaneously. At any time during power up, the supply voltages must be: 1.2 V < 1.8 V < 3.3 V.
3.6.3

82541PI(ER) Controller Power Supply Filtering

The 82541PI(ER) controller switches relatively high currents at high frequencies, requiring
generous use of both bulk capacitance and high speed decoupling capacitance adjacent to the
device.
Bypass capacitors for each power rail should be 0.1 µF. If possible, orient the capacitors close to
the device and adjacent to power pads. Decoupling capacitors should connect to the power and
ground planes with short, thick traces (15 mils or 0.4 mm or more), and 14 mil (3.5 mm) vias per
capacitor pad.
Furnish approximately 20 µF of bulk capacitance for each of the main 1.2 V and 1.8 V levels. This
can be easily achieved by using two 10 µF capacitors, placing them as close to the device power
connections as possible.
3.6.4

82541PI(ER) Controller Power Management and Wake Up

The 82541PI(ER) controller supports low power operation as defined in the PCI Bus Power
Management Specification. There are two defined power states, D0 and D3. The D0 state provides
full power operation and is divided into two sub-states: D0u (uninitialized) and D0a (active). The
D3 state provides low power operation and is also divided into two sub-states: D3hot and D3cold.
To enter the low power state, the software driver must stop data transmission and reception. Either
the operating system or the driver must program the Power Management Control/Status Register
(PMCSR) and the Wakeup Control Register (WUC). If wakeup is desired, the appropriate wakeup
LAN address filters must also be set. The initial power management settings are specified by
EEPROM bits.
When the 82541PI(ER) controller transitions to either of the D3 low power states, the 1.2 V, 1.8 V,
and 3.3 V sources must continue to be supplied to the device. Otherwise, it will not be possible to
use a wakeup mechanism. The AUX_POWER signal is a logic input to the 82541PI(ER) controller
that denotes auxiliary power is available. If AUX_POWER is asserted, the 82541PI(ER controller
advertises that it supports wake up from a D3cold state.
The 82541PI(ER) device supports both Advanced Power Management (APM) wakeup and
Advanced Configuration and Power Interface (ACPI) wakeup. APM wakeup has also been known
in the past as "Wake on LAN."
Wakeup uses the PME# signal to wake the system. PME# is an active low signal connected to a
GPIO port on the ICH5, ICH6, or ICH7 that goes active in response to receiving a Magic Packet*,
a network wake-up packet, or link status change indication. PME# remains asserted until it is
disabled through the Power Management Control/Status Register.
Application Note (AP-468)
82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
17