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82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
Figure 12. Using a Moat to Reduce Noise From Adjacent Traces and Power Fills
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Main Power Plane
4.5
82562GZ(GX) Signal Terminations
Two differential pairs are terminated using 54.9 Ω (1% tolerance) resistors, placed near the LAN
controller. One resistor connects to the MDI+ (MDI positive) signal trace and another resistor
connects to the MDI- (MDI negative) signal trace.
Termination resistor values were recently increased from 49.9 Ω to 54.9 Ω to improve return loss.
However, on some designs, this change caused the PCB's output amplitude to be slightly above the
peak-to-peak center of the IEEE specification. As a result, RBIAS resistor values were increased
(RBIAS10 549 to 619 Ω and RBIAS100 619 to 649 Ω) to reduce the PCB's output amplitude to
better meet the IEEE peak-to-peak center specification.
For 100Base-TX designs, the IEEE specification allows a -950 mVpk to -1050 mVpk for the
negative peak and +950 mVpk to +1050 mVpk for the positive peak. Ideally, a typical PCB output
amplitude should be within -975 mVpk to -1025 mVpk for the negative peak and +975 mVpk to
+1025 mVpk for the positive peak.
For 10Base-T designs, the IEEE specification allows a -2.2 mVpk to -2.8 mVpk for the negative
peak and +2.2 mVpk to +2.8 mVpk for the positive peak. Ideally, a typical PCB output amplitude
should be within -2.35 mVpk to -2.55 mVpk for the negative peak and +2.35 mVpk to +2.55 mVpk
for the positive peak.
The RBIAS values previously listed should be considered starting values. Intel recommends that
board designers measure each of their PCB's output amplitude and then adjust the RBIAS values as
required.
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30 mil moat or gap between main power plane and other power fill areas
Optional
Ferrite
Board
Power trace between 50 - 200 mills wide
Power trace between 50 - 200 mills wide
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Application Note (AP-468)
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