Distance B: Phy To Magnetics (Priority 2); Distance C: Lan Controller To Chipset (Priority 3); Distance D: The Overall Length Of Differential Traces From Lan To Rj-45 (Priority 4); Distance E: Ethernet Controller To Pcb Edge - Intel 82541PI Design Manual

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82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
4.2.2

Distance B: PHY to Magnetics (Priority 2)

Distance B in
82541PI(ER) and two inches between devices for the 82562GZ(GX). The high speed nature of the
signals propagating through these traces requires that the distance between these components are
closely observed. In general, any section of traces that is intended for use with high speed signals
should observe proper termination practices. Proper termination of signals can reduce reflections
caused by impedance mismatches between devices and traces.
The reflections of a signal may have a high frequency component that may contribute more EMI
than the original signal itself. For this reason, these traces should be designed to a 100 Ω
differential value.
4.2.3

Distance C: LAN Controller to Chipset (Priority 3)

The distance labeled "C" should be addressed separately between the 82541PI(ER) and the
82562GZ(GX).
4.2.3.1
LAN Connect Interface Distance for the 82562GZ(GX)
This section contains guidelines for LOM designs that comply with the LCI. These guidelines
should not be treated as a specification; however, it must be ensured that the system meets
specified timings. This can be verified through simulations or other techniques. The LCI can be
routed to support a 10/100 Mbps LOM solution with 82562GZ(GX) devices.
Distance C, the LCI, should be less than 10 inches.
4.2.3.2
PCI Interface for the 82541PI(ER)
The PCI bus on 82541PI(ER) meets PCI 2.3 specification and operate as PCI slave devices for
configuration and register programming. After the controllers have been properly initialized, they
can also operate as PCI masters to fetch memory descriptors and to read/write data buffers.
The controllers are capable of operating in either a 5 V or 3.3 V signaling environment. The VIO
terminals can be connected to either 3.3 V or 5 V to choose the appropriate PCI bus levels.These
connections bias the controller PCI I/O buffers for the correct switching strength. However, all
other digital inputs and outputs use 3.3 V signaling unless specified separately.
4.2.4
Distance D: The Overall Length of Differential Traces from LAN to RJ-
45 (Priority 4)
The overall length of differential pairs should be less than four inches measured from the LAN
controller to RJ-45 through the magnetics module.
The lengths of the differential traces (within each pair) should be equal within 50 mils (1.25 mm)
and as symmetrical as possible.
4.2.5

Distance E: Ethernet Controller to PCB Edge

The Ethernet controller should be placed at least one inch from the PCB edge (two inches is
preferred).
28
Figure 5
should also be designed to extend less than one inch between devices for the
Application Note (AP-468)

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