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R
Table 13: BPI Pins (Cont'd)
J47 is a three-pin header that allows users to connect the OE signal to V
pin. Jumper pin 1 to 2 connects the OE signal to VCC. Jumper pin 2 to 3 connects the OE
signal to an FPGA IOB.
J54 allows users to connect the revision select (RS) signals to the highest address lines of the
BPI device. Jumper pins 1 to 3 and pins 2 to 4 connect address 23 and address 24 to FPGA
IOBs. Jumper pins 3 to 5 and pins 4 to 6 connect RS0 and RS1 to the highest address lines
of the BPI device. See the Virtex-5 FPGA Configuration User Guide
information on how the RS signals can be applied in a user's application.
Virtex-5 LXT/SXT/FXT FPGA Prototype Platform
UG229 (v3.0.1) May 21, 2008
Label
FF665
A12
F18
A13
F14
A14
F15
A15
F17
A16
G17
A17
G14
A18
H13
A19
G16
A20
G15
A21
Y18
A22
AA18
A23
Y11
A24
AA10
WE_N
AA17
WP_N
Y5
ADV_N
Y6
RST_N
K7
CE_N
Y12
WAIT
K6
CLK
U5
OE_N
AA12
Table 13
shows the corresponding FPGA pin.
www.xilinx.com
Pin Number For Package Type
FF1136
G22
J15
K16
K21
J22
L16
L15
L20
L21
AE23
AE22
AG12
AF13
AF20
M5
M6
U7
AE14
T8
J7
AF14
Detailed Description
FF1738
P27
N16
M16
N26
P26
P17
P18
P25
N25
AM29
AL30
AK14
AK15
AM28
AA6
AA7
N6
AL14
N5
U6
AM13
or to an FPGA
CC
[Ref 3]
for more
27
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