Flash Rom Timing; Flash Rom Read Cycle Timing - LSI LSI53C1030 Technical Manual

5.4.2 Flash ROM Timing

5-16
Table 5.18 and Figure 5.10
read accesses.
Table 5.18

Flash ROM Read Cycle Timing

Symbol Parameter
t Address setup to FLSHALE/ HIGH
1
t Address hold from FLSHALE/ HIGH
2
t FLSHALE/ pulse width
3
t Address valid to data clocked in
4
t FLSHCE/ LOW to data clocked in
5
t MOE/ LOW to data clocked in
6
t Data setup to MOE/ HIGH
7
t Data setup to FLSHCE/ HIGH
8
t Data hold from FLSHCE/ HIGH
9
Specifications
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
provide the timing information for Flash ROM
Min Max Unit
25 – ns
25 – ns
25 – ns
135 – ns
85 – ns
75 – ns
10 – ns
10 – ns
0 – ns