Xycom XVME-240 Manual page 59

XVME-240 Manual
October, 1984
Connector
Signal
Pin Number
Mnemonic
1A: 10
SYSCLK
lC: 10
SYSFAIL*
SYSRESET* 1C:12
1A:14
WRITE*
+5V STDBY IB: 31
1A: 32
+5v
1B: 32
lC: 32
lC: 31
+12v
-12v 1A: 31
Table B-l. VMEbus Signal Identification (cont'd)
and
SYSTEM CLOCK - A constant 16-MHz clock signal
that is independent of processor speed or timing.
This signal is used for general system timing use.
SYSTEM FAIL - Open-collector
indicates that a failure has occurred in the system.
This signal may be generated by any module on the
VMEbus.
SYSTEM RESET - Open-collector driven signal
which, when low, will cause the system to be reset.
WRITE - Three-state driven signal that specifies
the data transfer cycle in progress to be either
read or written.
operation; a low level indicates a write operation.
+5 Vdc STANDBY - This line supplies +5 Vdc to
devices requiring battery backup.
+5 Vdc Power - Used by system logic circuits.
+12 Vdc Power - Used by system logic circuits.
- 12 Vdc Power - Used by system logic circuits.
Signal Name and Description
A high level indicates a read
B-4
driven signal that