Xycom XVME-240 Manual page 32

XVME-240 Manual
October, 1984
3.3.2 Module Status/Control Register (Base Address+081H)
A major feature of the XYCOM Standard I/O Architecture is the inclusion of an 8-bit
status and control register on all intelligent and non-intelligent I/O modules. On the
DIO module (a non-intelligent module) this register provides the user with two
indicator bits which control the current status of the self-test LEDs on the front
panel, an interrupt pending bit, an interrupt enable bit, a module soft reset bit, and
three read/write flag bits which can be employed by the user as software flags. The
Status/Control register is accessed at the module base address + offset 081H. Figure
3-2 shows the register bit definitions for the DIO Status/Control byte.
STATUS/CONTROL REGISTER (Base Address + 081H)
The following list defines the individual bit positions in the Status/Control register:
Read/Write
Bit 7,Bit 6,
Bit 5:
Bit 4: Read/Write
Read/Write
Bit 3:
Figure Status/Control Register
3-2.
These bits are available to the user to be employed as
general purpose flags.
This bit is for a software module reset.
"toggled" between a logic "0" and a "1" (i.e., if it is set
from 0 to 1 and then back to 0) the module will reset in
the following fashion:
1) The interrupt mask register will be cleared (all
inputs masked out).
2) All ports will be configured as inputs.
3) All port latches are reset to 00H.
4) All flag outputs are reset to 00H.
This bit must be set to a logic "1" in order for the
module interrupt capability to be enabled.
3-5
- Red LED* (SYSFAIL*)
Interrupt Pending
Interrupt Enable
Software
User Available Flag Bits
Reset
If it is