Xycom XVME-240 Manual page 39

XVME-240 Manual
October, 1984
Interrupts Pending register shows which interrupts in particular (input lines) are
pending.
As mentioned in the previous section (Section 3.3.6), the contents of the interrupt
latch and the Interrupt Mask Register are logically ANDed. The Interrupts
input
Pending Register contains the result of this AND operation for each interrupt input
line.
bit in the Interrupts Pending Register corresponds to one of the interrupt input
Each
lines. Figure 3-7 is a bit map of the Interrupts Pending Register.
INTERRUPTS PENDING REGISTER (Base Address + 82H)
.
Bit Bit
Bit
7 6 5
Logic " 1 " = A Pending Interrupt.
Logic " 0 " = No Pending Interrupt.
When reading the Interrupts Pending Register (Base address + 82H),
"1" means that the corresponding interrupt input has a pending interrupt.
register bit is set to " 0 " it means that the corresponding interrupt input has no pending
interrupt.
It is possible for several interrupt inputs to have interrupts pending at one time. In
this case, the user software/firmware will have to prioritize the interrupting devices
to establish an interrupt handling order.
3.3.8 Interrupt Vector Register
This read/write register is used to hold the interrupt service vector which will be
transmitted to the system processor during the interrupt acknowledge sequence,
allowing automatic entry into a service routine without device polling. This is an 8-bit
register arranged with the MSB and the LSB as shown in Figure 3-8.
Bit Bit Bit Bit
3
4
2 1
Figure 3-7. Interrupts Pending Register
(Base Address + 85H)
3-12
Bit
l
0
Interrupt Input 4
Interrupt Input 5
Interrupt Input 6
Interrupt Input 7
a bit containing a
When a
.