Xycom XVME-240 Manual page 36

XVME-240 Manual
October, 1984
When an interrupt signal has been detected and latched by an interrupt input, the bit
corresponding to that interrupt input in the Interrupt Input Register will be set to logic
"1". This bit will remain set until the interrupt input latch is properly cleared by
the Interrupt Clear Register (for information using the Interrupt Clear
to Section 3.3.5).
SYSRESET and Soft Reset do not clear the Interrupt
Input Register. After power-up and reset, prior to
enabling interrupts, this register should be cleared
by using the Interrupt Clear Register.
When the interrupt input latch has been cleared, and when an interrupt input has not
yet detected and latched an interrupt signal, the bit corresponding to that interrupt
input will be a logic "0".
3.3.5 Interrupt Clear Register (Base Address + 84H)
The Interrupt Clear Register provides the user with the means to clear interrupt input
latches and registers. These latches and registers will have to be cleared after power-
up
or reset prior to enabling interrupts, and immediately following completion of user-
provided interrupt service routines.
As mentioned in the' previous section, each interrupt input has its own Interrupt Edge
Detection circuitry and Interrupt Latch. Once an input has detected and latched and
interrupt, the latch will remain set to a logic "1" until the latch is cleared.
the interrupt input latches is accomplished by using the
Figure 3-5 shows a bit map of the "write only" Interrupt Clear
INTERRUPT CLEAR REGISTER (Base Address + 84H)
Bit Bit Bit
7 6 5
I
Figure 3-5. Interrupt Clear Register
NOTE
Interrupt Input Latch 4
Interrupt Input Latch 5
Interrupt Input Latch 6
Interrupt Input Latch 7
3-9
Register
Clearing
Interrupt Clear Register.
Register.
using
refer