Xycom XVME-240 Manual page 43

XVME-240 Manual
October, 1984
The Interrupt Input signal is buffered before it reaches the Edge Detection circuitry.
Depending upon how the Edge Detection Jumper is set, the Interrupt Input signal will
be gated in on either its rising or falling edge (refer to Section 2,4.8). After the
Interrupt Input signal is gated through the Edge Detection circuitry, it can be latched
(providing the Interrupt Input latch is cleared). The clear line on the Interrupt Input
latch corresponds to a particular bit in the Interrupt Clear register. By writing a "1"
to the corresponding bit in the Interrupt Clear register, an Interrupt Input latch can be
cleared (refer to Section 3.3.5).
The output of the Interrupt Input latch goes directly to its corresponding bit in the
Interrupt Input Register. Thus, the Interrupt Input Register reflects the status of the
Interrupt Input latch and not the current state of the Interrupt Input line itself (refer
to Section 3.3.4 for more information on the Interrupt Input Register). The Interrupt
Input Register can be read by user software/firmware to determine which Interrupt
Inputs have actually latched an interrupt from an external device. When an Interrupt
Input
latch is cleared, the Interrupt Input Register bit for that latch is also cleared.
The output of the Interrupt Input latch also goes to the input of an "AND" gate, where
it is logically "ANDed" with the corresponding Interrupt Mask Register bit for this
Interrupt Input line (refer to Figure 3-10). If the Interrupt Mask bit for an Interrupt
Input is set to a logic "1" it will "pass" an interrupt through the mask. If the Interrupt
Mask bit for an Interrupt Input is written a logic "0" it will mask out the interrupt
signal and temporarily prevent it from generating a VMEbus Interrupt Request. Notice
that the Interrupt Mask bit does not clear the Interrupt latch, it merely keeps the
latched signal from going any farther than the
latched while the corresponding mask bit is set to "0", it will be prevented from
passing through the mask; but, if the same mask bit is written a "1" before the latch is
cleared, the interrupt signal will pass through the mask. On power-up or system reset
the Interrupt Mask Register is automatically set so that all bits contain a "0". Thus,
user software/firmware will enable the desired Interrupt Input lines by writing new
masks to the Interrupt Mask Register as they are needed.
The Interrupt Pending Register Bit is located immediately following the point where
the Interrupt Input latch output and the Interrupt Mask Register bit are logically
"ANDed"
If an interrupt signal is passed through an Interrupt Mask, it will set this bit
(Le., logic "1"), thus, indicating that this particular interrupt line is ready to generate
an Interrupt Request to the system processor. This register bit is related to bit 2 of
the Status/Control Register (refer to Section 3.3.2). When bit 2 of the Status/Control
Register is set, it indicates that one or more of the Interrupt Input lines have interrupt
pending. Figure 3-10 shows that the Interrupt Pending Flag (bit 2 of the
Status/Control Register) is set whenever 1 of the 8 inputs to an 8 input " O R " gate is
set high. Thus, user software/firmware could read bit 2 of the Status/Control register
to determine if there are any pending interrupt at all, and then read the Interrupt
Pending Register to determine which particular input lines are transmitting the
interrupts.
As mentioned in the previous paragraph, the Interrupt Input lines are all logically
"ORed" to produce a single output. This output determines the state of the Interrupt
Pending Flag (bit 2 of the Status/Control Register) and is also logically "ANDed"
bit 3 of the Status/Control Register (Le., the Interrupt Enable Bit). The Interrupt
Enable Bit is the "master"
by the DIO module (refer to Section 3.3.2 for information on
Status/Control Register). If a logic "1" is written to the Interrupt Enable bit, the
interrupt capability of the DIO module is enabled. If a logic "0" is written to the
Interrupt
control bit for enabling/disabling the interrupts generated
3-16
"AND" gate. Thus, if an interrupt is
with
the
accessing