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Renesas SuperH RISC engine Series Manuals
Manuals and User Guides for Renesas SuperH RISC engine Series. We have
1
Renesas SuperH RISC engine Series manual available for free PDF download: Hardware Manual
Renesas SuperH RISC engine Series Hardware Manual (739 pages)
32-Bit RISC Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 4.56 MB
Table of Contents
Configuration of this Manual
6
General Precautions on Handling of Product
5
Table of Contents
6
2 Configuration Ofthis Manual
7
Preface
7
Table of Contents
19
Contents
19
Asthefinal Partof Eachsection.
31
List of Registers
31
Electrical Characteristics
38
Appendix
41
Section 1 Overview
47
SH7705 Features
47
Block Diagram
52
Figure 1.1 Block Diagram of SH7705
52
Pin Assignment
53
Figure 1.2 Pin Assignment (FP-208C)
53
Index
53
Figure 1.3 Pin Assignment (TBP-208A)
54
Table 1.2 Pin Functions
55
Pin Functions
63
Table 1.3 Pin Functions
63
Section 2 CPU
71
Processing States and Processing Modes
71
Processing States
71
Processing Modes
72
Figure 2.1 Processing State Transitions
72
Memory Map
73
Logical Address Space
73
External Memory Space
74
Table 2.1 Logical Address Space
74
Register Descriptions
75
Figure 2.2 Logical Address to External Memory Space Mapping
75
Table 2.2 Register Initial Values
76
Figure 2.3 Register Configuration in each Processing Mode
77
General Registers
78
System Registers
79
Figure 2.4 General Registers
79
Program Counter
80
Figure 2.5 System Registers and Program Counter
80
Control Registers
81
Data Formats
83
Register Data Format
83
Figure 2.6 Control Register Configuration
83
Memory Data Formats
84
Figure 2.7 Data Format on Memory (Big Endian Mode)
84
Figure 2.8 Data Format on Memory (Little Endian Mode)
85
Features of CPU Core Instructions
86
Instruction Execution Method
86
CPU Instruction Addressing Modes
88
Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions
88
CPU Instruction Formats
91
Table 2.4 CPU Instruction Formats
91
Instruction Set
94
CPU Instruction Set Based on Functions
94
Table 2.5 CPU Instruction Types
94
Table 2.6 Data Transfer Instructions
98
Table 2.7 Arithmetic Operation Instructions
100
Table 2.8 Logic Operation Instructions
102
Table 2.9 Shift Instructions
103
Table 2.10 Branch Instructions
104
Table 2.11 System Control Instructions
105
Operation Code Map
108
Table 2.12 Operation Code Map
108
Section 3 Memory Management Unit (MMU)
111
Role of MMU
111
Figure 3.1 MMU Functions
112
MMU of this LSI
113
Figure 3.2 Virtual Address Space (MMUCR.AT = 1)
114
Figure 3.3 Virtual Address Space (MMUCR.AT = 0)
115
Figure 3.4 P4 Area
115
Figure 3.5 External Memory Space
116
Register Descriptions
118
Page Table Entry Register High (PTEH)
118
Page Table Entry Register Low (PTEL)
119
Translation Table Base Register (TTB)
119
MMU Control Register (MMUCR)
119
TLB Functions
121
Configuration of the TLB
121
Figure 3.6 Overall Configuration of the TLB
121
Figure 3.7 Virtual Address and TLB Structure
122
TLB Indexing
123
Figure 3.8 TLB Indexing (IX = 1)
123
TLB Address Comparison
124
Figure 3.9 TLB Indexing (IX = 0)
124
Figure 3.10 Objects of Address Comparison
125
Page Management Information
126
Table 3.1 Access States Designated by D, C, and PR Bits
126
MMU Functions
127
MMU Hardware Management
127
MMU Software Management
127
MMU Instruction (LDTLB)
128
Figure 3.11 Operation of LDTLB Instruction
128
Avoiding Synonym Problems
129
Figure 3.12 Synonym Problem (32-Kbyte Cache)
130
Section 4 Cache
130
MMU Exceptions
131
TLB Miss Exception
131
TLB Protection Violation Exception
132
TLB Invalid Exception
133
Initial Page Write Exception
134
Figure 3.13 MMU Exception Generation Flowchart
135
Memory-Mapped TLB
136
Address Array
136
Data Array
136
Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access
137
Usage Examples
138
Usage Note
138
Section 4 Cache
139
Features
139
Cache Structure
139
Table 4.1 Number of Entries and Size/Way in each Cache Size
139
Figure 4.1 Cache Structure (32-Kbyte Mode)
140
Register Descriptions
141
Table 4.2 LRU and Way Replacement (When Cache Locking Mechanism Is Disabled)
141
Cache Control Register 1 (CCR1)
142
Cache Control Register 2 (CCR2)
143
Table 4.3 Way Replacement When a PREF Instruction Misses the Cache
145
Table 4.4 Way Replacement When Instructions Other than the PREF Instruction Miss the Cache
145
Table 4.5 LRU and Way Replacement (When W2LOCK = 1 and W3LOCK = 0)
145
Table 4.6 LRU and Way Replacement (When W2LOCK = 0 and W3LOCK = 1)
145
Cache Control Register 3 (CCR3)
146
Table 4.7 LRU and Way Replacement (When W2LOCK = 1 and W3LOCK = 1)
146
Operation
147
Searching the Cache
147
Figure 4.2 Cache Search Scheme
147
Read Access
148
Prefetch Operation
148
Write Access
148
Write-Back Buffer
149
Coherency of Cache and External Memory
149
Figure 4.3 Write-Back Buffer Configuration
149
Memory-Mapped Cache
150
Address Array
150
Data Array
151
Figure 4.4 Specifying Address and Data for Memory-Mapped Cache Access (32-Kbyte Mode)
152
Table 4.8 Address Format Based on Size of Cache to be Assigned to Memory
152
Usage Examples
153
Usage Note
154
Section 5 Exception Handling
155
Register Descriptions
155
TRAPA Exception Register (TRA)
156
Figure 5.1 Register Bit Configuration
156
Exception Event Register (EXPEVT)
157
Interrupt Event Register (INTEVT)
157
Interrupt Event Register 2 (INTEVT2)
158
Exception Address Register (TEA)
158
Exception Handling Function
159
Exception Handling Flow
159
Exception Vector Addresses
160
Exception Codes
160
Exception Request and BL Bit (Multiple Exception Prevention)
160
Exception Source Acceptance Timing and Priority
161
Table 5.1 Exception Event Vectors
162
Individual Exception Operations
164
Resets
164
General Exceptions
164
General Exceptions (MMU Exceptions)
167
Usage Notes
170
Section 6 Interrupt Controller (INTC)
171
Features
171
Figure 6.1 Block Diagram of INTC
172
Input/Output Pins
173
Register Descriptions
173
Table 6.1 Pin Configuration
173
Interrupt Priority Level Setting Registers a to H (IPRA to IPRH)
174
Table 6.2 Interrupt Sources and IPRA to IPRH
174
Interrupt Control Register 0 (ICR0)
175
Interrupt Control Register 1 (ICR1)
176
Interrupt Control Register 2 (ICR2)
178
PINT Interrupt Enable Register (PINTER)
178
Interrupt Request Register 0 (IRR0)
179
Interrupt Request Register 1 (IRR1)
180
Interrupt Request Register 2 (IRR2)
181
Interrupt Sources
182
NMI Interrupt
182
IRQ Interrupts
182
IRL Interrupts
183
Figure 6.2 Example of IRL Interrupt Connection
183
PINT Interrupt
184
On-Chip Peripheral Module Interrupts
184
Interrupt Exception Handling and Priority
185
Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)
186
Operation
190
Interrupt Sequence
190
Figure 6.3 Interrupt Operation Flowchart
192
Multiple Interrupts
193
Usage Note
193
Section 7 Bus State Controller (BSC)
195
Overview
195
Features
195
Block Diagram
196
Figure 7.1 BSC Functional Block Diagram
196
Pin Configuration
197
Table 7.1 Pin Configuration
197
Area Overview
198
Address Map
198
Table 7.2 Physical Address Space Map
198
Memory Bus Width
200
Figure 7.2 Address Space
200
Table 7.3 Correspondence between External Pins (MD3 and MD4) and Memory Size
200
Shadow Space
201
Register Descriptions
201
Common Control Register (CMNCR)
202
Csn Space Bus Control Register (Csnbcr) (N = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
204
SDRAM Control Register (SDCR)
220
Refresh Timer Control/Status Register (RTCSR)
223
Refresh Timer Counter (RTCNT)
225
Refresh Time Constant Register (RTCOR)
225
Reset Wait Counter (RWTCNT)
226
Endian/Access Size and Data Alignment
226
Table 7.4 32-Bit External Device/Big Endian Access and Data Alignment
227
Table 7.5 16-Bit External Device/Big Endian Access and Data Alignment
228
Table 7.6 8-Bit External Device/Big Endian Access and Data Alignment
229
Table 7.7 32-Bit External Device/Little Endian Access and Data Alignment
230
Table 7.8 16-Bit External Device/Little Endian Access and Data Alignment
231
Table 7.9 8-Bit External Device/Little Endian Access and Data Alignment
232
Normal Space Interface
233
Basic Timing
233
Figure 7.3 Continuous Access for Normal Space (no Wait, WM Bit in Csnwcr = 1, 16-Bit Bus Width, Longword Access, no Wait State between Cycles)
234
Figure 7.4 Continuous Access for Normal Space (no Wait, One Wait State between Cycles)
235
Figure 7.5 Example of 32-Bit Data-Width SRAM Connection
236
Figure 7.6 Example of 16-Bit Data-Width SRAM Connection
237
Figure 7.7 Example of 8-Bit Data-Width SRAM Connection
237
Access Wait Control
238
Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only)
238
Figure 7.9 Wait State Timing for Normal Space Access (Wait State Insertion by W a I T Signal)
239
C S N Assert Period Expansion
240
Address/Data Multiplex I/O Interface
241
Figure 7.11 Access Timing for MPX Space (Address Cycle no Wait, Data Cycle no Wait)
241
Figure 7.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle no Wait)
242
Figure 7.13 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)
243
SDRAM Interface
244
SDRAM Direct Connection
244
Figure 7.14 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Data Bus)
245
Address Multiplexing
246
Figure 7.15 Example of 64-Mbit Synchronous DRAM (16-Bit Data Bus)
246
Table 7.10 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (1)-1
247
Table 7.11 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (2)-1
249
Table 7.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (3)
251
Table 7.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (4)-1
252
Table 7.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (5)-1
254
Table 7.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (6)-1
256
Burst Read
258
Table 7.16 Relationship between Access Size and Number of Bursts
258
Figure 7.16 Synchronous DRAM Burst Read Wait Specification Timing (Auto Precharge)
259
Single Read
260
Figure 7.17 Basic Timing for Single Read (Auto Precharge)
260
Burst Write
261
Figure 7.18 Basic Timing for Synchronous DRAM Burst Write (Auto Precharge)
262
Single Write
263
Figure 7.19 Basic Timing for Single Write (Auto Precharge)
263
Bank Active
264
Figure 7.20 Burst Read Timing (no Auto Precharge)
265
Figure 7.21 Burst Read Timing (Bank Active, same Row Address)
266
Figure 7.22 Burst Read Timing (Bank Active, Different Row Addresses)
267
Figure 7.23 Single Write Timing (no Auto Precharge)
268
Figure 7.24 Single Write Timing (Bank Active, same Row Address)
269
Figure 7.25 Single Write Timing (Bank Active, Different Row Addresses)
270
Refreshing
271
Figure 7.26 Auto-Refresh Timing
272
Figure 7.27 Self-Refresh Timing
273
Low-Frequency Mode
274
Figure 7.28 Low-Frequency Mode Access Timing
274
Power-On Sequence
275
Table 7.17 Access Address in SDRAM Mode Register Write
275
Burst ROM Interface
277
Figure 7.29 Synchronous DRAM Mode Write Timing (Based on JEDEC)
277
Figure 7.30 Burst ROM Access (Bus Width 8 Bits, Access Size 32 Bits (Number of Burst 4), Access Wait for the 1St Time 2, Access Wait for 2Nd Time and after 1)
278
Table 7.18 Relationship between Bus Width, Access Size, and Number of Bursts
278
Byte-Selection SRAM Interface
279
Figure 7.31 Byte-Selection SRAM Basic Access Timing
279
Figure 7.32 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM
280
Figure 7.33 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM
280
Wait between Access Cycles
281
Bus Arbitration
281
Others
283
Figure 7.34 Bus Arbitration
283
Section 8 Direct Memory Access Controller (DMAC)
285
Features
285
Figure 8.1 Block Diagram of DMAC
286
Input/Output Pins
287
Register Descriptions
287
Table 8.1 Pin Configuration
287
DMA Source Address Registers (SAR)
288
DMA Destination Address Registers (DAR)
288
DMA Transfer Count Registers (DMATCR)
289
DMA Channel Control Registers (CHCR)
289
DMA Operation Register (DMAOR)
294
DMA Extended Resource Selectors 0, 1 (DMARS0, DMARS1)
296
Table 8.2 Transfer Request Sources
297
Operation
298
Transfer Flow
298
Figure 8.2 DMAC Transfer Flowchart
299
DMA Transfer Requests
300
Table 8.3 Selecting External Request Modes with RS Bits
300
Table 8.4 Selecting External Request Detection with DL, DS Bits
301
Table 8.5 Selecting External Request Detection with DO Bit
301
Table 8.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
302
Table 8.7 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
302
Channel Priority
303
Figure 8.3 Round-Robin Mode
304
Figure 8.4 Channel Priority in Round-Robin Mode
305
DMA Transfer Types
306
Table 8.8 Supported DMA Transfers
306
Figure 8.5 Data Flow of Dual Address Mode
307
Figure 8.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory)
308
Figure 8.7 Data Flow in Single Address Mode
309
Figure 8.8 Example of DMA Transfer Timing in Single Address Mode
309
Figure 8.9 DMA Transfer Example in Cycle-Steal Normal Mode
310
Figure 8.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
311
Figure 8.11 DMA Transfer Example in Burst Mode
311
Table 8.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category
312
Number of Bus Cycle States and DREQ Pin Sampling Timing
313
Section 2 CPU
313
Figure 8.12 Bus State When Multiple Channels Are Operating
313
Figure 8.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
313
Figure 8.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
314
Figure 8.15 Example of DREQ Input Detection in Burst Mode Edge Detection
314
Figure 8.16 Example of DREQ Input Detection in Burst Mode Level Detection
315
Figure 8.17 Example of DMA Transfer End Signal (in Cycle Steal Level Detection)
315
Precautions
316
Precautions When Mixing Cycle-Steal Mode Channels and Burst Mode Channels
316
Figure 8.18 BSC Ordinary Memory Access (no Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
316
Section 9 Clock Pulse Generator (CPG)
317
Features
317
Figure 9.1 Block Diagram of Clock Pulse Generator
318
Input/Output Pins
320
Table 9.1 Clock Pulse Generator Pins and Functions
320
Clock Operating Modes
321
Table 9.2 Clock Operating Modes
321
Table 9.3 Possible Combination of Clock Modes and FRQCR Values
322
Register Descriptions
325
Frequency Control Register (FRQCR)
325
USB Clock Frequency Control Register (UCLKCR)
327
Usage Notes
327
Changing Frequency
328
Changing Multiplication Rate
328
Changing Division Ratio
328
Modification of Clock Operating Mode
328
Usage Notes
329
Figure 9.2 Points for Attention When Using Crystal Resonator
329
Figure 9.3 Points for Attention When Using PLL Oscillator Circuit
330
Section 10 Watchdog Timer (WDT)
331
Features
331
Register Descriptions
332
Watchdog Timer Counter (WTCNT)
332
Figure 10.1 Block Diagram of WDT
332
Watchdog Timer Control/Status Register (WTCSR)
333
Notes on Register Access
335
Operation
336
Canceling Software Standbys
336
Figure 10.2 Writing to WTCNT and WTCSR
336
Changing Frequency
337
Using Watchdog Timer Mode
337
Using Interval Timer Mode
337
Section 11 Power-Down Modes
339
Features
339
Table 11.1 States of Power-Down Modes
340
Input/Output Pins
341
Register Descriptions
341
Table 11.2 Pin Configuration
341
Standby Control Register (STBCR)
342
Standby Control Register 2 (STBCR2)
343
Standby Control Register 3 (STBCR3)
344
Sleep Mode
345
Transition to Sleep Mode
345
Canceling Sleep Mode
345
Software Standby Mode
346
Transition to Software Standby Mode
346
Canceling Software Standby Mode
346
Module Standby Function
347
Transition to Module Standby Function
347
Figure 11.1 Canceling Standby Mode with STBY Bit in STBCR
347
Canceling Module Standby Function
348
Hardware Standby Mode
348
Transition to Hardware Standby Mode
348
Canceling Hardware Standby Mode
348
Timing of STATUS Pin Changes
349
Figure 11.2 Power-On Reset STATUS Output
349
Figure 11.3 Manual Reset STATUS Output
349
Figure 11.4 Canceling Software Standby by Interrupt STATUS Output
350
Figure 11.5 Canceling Software Standby by Power-On Reset STATUS Output
350
Figure 11.6 Canceling Software Standby by Manual Reset STATUS Output
351
Figure 11.7 Canceling Sleep by Interrupt STATUS Output
351
Figure 11.8 Canceling Sleep by Power-On Reset STATUS Output
352
Figure 11.9 Canceling Sleep by Manual Reset STATUS Output
352
Figure 11.10 Hardware Standby Mode (When CA Goes Low in Normal Operation)
353
Figure 11.11 Hardware Standby Mode Timing (When CA Goes Low During WDT Operation While Standby Mode Is Canceled)
353
Section 12 Timer Unit (TMU)
355
Features
355
Figure 12.1 TMU Block Diagram
356
Input/Output Pin
357
Register Descriptions
357
Table 12.1 Pin Configuration
357
Timer Start Register (TSTR)
358
Timer Control Registers (TCR)
359
Timer Constant Registers (TCOR)
363
Timer Counters (TCNT)
363
Input Capture Register_2 (TCPR_2)
363
Operation
364
Counter Operation
364
Figure 12.2 Setting Count Operation
364
Figure 12.3 Auto-Reload Count Operation
365
Figure 12.4 Count Timing When Internal Clock Is Operating
365
Input Capture Function
366
Figure 12.5 Count Timing When External Clock Is Operating (both Edges Detected)
366
Figure 12.6 Operation Timing When Using Input Capture Function
366
Interrupts
367
Status Flag Set Timing
367
Status Flag Clear Timing
367
Figure 12.7 UNF Set Timing
367
Figure 12.8 Status Flag Clear Timing
367
Interrupt Sources and Priorities
368
Usage Notes
368
Writing to Registers
368
Reading Registers
368
Table 12.2 TMU Interrupt Sources
368
Section 13 Compare Match Timer (CMT)
369
Features
369
Figure 13.1 CMT Block Diagram
369
Register Descriptions
370
Compare Match Timer Start Register (CMSTR)
370
Compare Match Timer Control/Status Register (CMCSR)
371
Compare Match Counter (CMCNT)
372
Compare Match Constant Register (CMCOR)
372
Operation
372
Period Count Operation
372
Figure 13.2 Counter Operation
372
CMCNT Count Timing
373
Compare Match Flag Set Timing
373
Figure 13.3 Count Timing
373
Figure 13.4 CMF Set Timing
373
Section 14 16-Bit Timer Pulse Unit (TPU)
375
Features
375
Table 14.1 TPU Functions
376
Figure 14.1 Block Diagram of TPU
377
Input/Output Pins
378
Register Descriptions
378
Table 14.2 Pin Configuration
378
Timer Control Registers (TCR)
380
Table 14.3 TPU Clock Sources
381
Table 14.4 TPSC2 to TPSC0 (1)
381
Table 14.4 TPSC2 to TPSC0 (2)
381
Table 14.4 TPSC2 to TPSC0 (3)
382
Table 14.4 TPSC2 to TPSC0 (4)
382
Timer Mode Registers (TMDR)
383
Timer I/O Control Registers (TIOR)
384
Table 14.5 IOA2 to IOA0
384
Timer Interrupt Enable Registers (TIER)
385
Timer Status Registers (TSR)
386
Timer Counters (TCNT)
387
Timer General Registers (TGR)
387
Timer Start Register (TSTR)
387
Operation
388
Overview
388
Basic Functions
389
Figure 14.2 Example of Counter Operation Setting Procedure
389
Figure 14.3 Free-Running Counter Operation
390
Figure 14.4 Periodic Counter Operation
390
Figure 14.5 Example of Setting Procedure for Waveform Output by Compare Match
391
Figure 14.6 Example of 0 Output/1 Output Operation
391
Buffer Operation
392
Figure 14.7 Example of Toggle Output Operation
392
Figure 14.8 Compare Match Buffer Operation
392
Table 14.6 Register Combinations in Buffer Operation
392
Figure 14.9 Example of Buffer Operation Setting Procedure
393
PWM Modes
394
Figure 14.10 Example of Buffer Operation
394
Figure 14.11 Example of PWM Mode Setting Procedure
395
Figure 14.12 Example of PWM Mode Operation (1)
396
Figure 14.13 Examples of PWM Mode Operation (2)
396
Section 15 Realtime Clock (RTC)
397
Features
397
Figure 15.1 RTC Block Diagram
398
Input/Output Pins
399
Register Descriptions
399
Table 15.1 Pin Configuration
399
64-Hz Counter (R64CNT)
400
Second Counter (RSECCNT)
400
Minute Counter (RMINCNT)
401
Hour Counter (RHRCNT)
401
Day of Week Counter (RWKCNT)
402
Date Counter (RDAYCNT)
403
Month Counter (RMONCNT)
403
Year Counter (RYRCNT)
404
Second Alarm Register (RSECAR)
404
Minute Alarm Register (RMINAR)
405
Hour Alarm Register (RHRAR)
406
Day of Week Alarm Register (RWKAR)
407
Date Alarm Register (RDAYAR)
408
Month Alarm Register (RMONAR)
409
Year Alarm Register (RYRAR)
410
RTC Control Register 1 (RCR1)
411
RTC Control Register 2 (RCR2)
412
RTC Control Register 3 (RCR3)
414
Operation
415
Initial Settings of Registers after Power-On
415
Setting Time
415
Figure 15.2 Setting Time
415
Reading the Time
416
Figure 15.3 Reading the Time
416
Alarm Function
417
Figure 15.4 Using the Alarm Function
417
Crystal Oscillator Circuit
418
Figure 15.5 Example of Crystal Oscillator Circuit Connection
418
Table 15.2 Recommended Oscillator Circuit Constants (Recommended Values)
418
Notes for Usage
419
Register Writing During RTC Count
419
Use of Realtime Clock (RTC) Periodic Interrupts
419
Standby Mode after Register Setting
419
Figure 15.6 Using Periodic Interrupt Function
419
Section 16 Serial Communication Interface with FIFO (SCIF)
421
Features
421
Figure 16.1 Block Diagram of SCIF
423
Input/Output Pins
424
Table 16.1 Pin Configuration
424
Register Descriptions
425
Receive Shift Register (SCRSR)
426
Receive FIFO Data Register (SCFRDR)
426
Transmit Shift Register (SCTSR)
426
Transmit FIFO Data Register (SCFTDR)
427
Serial Mode Register (SCSMR)
427
Serial Control Register (SCSCR)
431
FIFO Error Count Register (SCFER)
435
Serial Status Register (SCSSR)
436
Bit Rate Register (SCBRR)
441
FIFO Control Register (SCFCR)
444
FIFO Data Count Register (SCFDR)
447
Transmit Data Stop Register (SCTDSR)
447
Operation
448
Overview
448
Asynchronous Mode
448
Table 16.2 SCSMR Settings for Serial Transfer Format Selection
449
Serial Operation in Asynchronous Mode
450
Table 16.3 Serial Transfer Formats
450
Figure 16.2 Sample SCIF Initialization Flowchart
452
Figure 16.3 Sample Serial Transmission Flowchart
453
Figure 16.4 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit)
455
Figure 16.5 Example of Transmit Data Stop Function
455
Figure 16.6 Transmit Data Stop Function Flowchart
456
Figure 16.7 Sample Serial Reception Flowchart (1)
457
Figure 16.8 Sample Serial Reception Flowchart (2)
458
Figure 16.9 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)
460
Clock Synchronous Mode
461
Serial Operation in Clock Synchronous Mode
462
Figure 16.12 Data Format in Clock Synchronous Communication
462
Figure 16.13 Sample SCIF Initialization Flowchart (1) (Transmission)
464
Figure 16.13 Sample SCIF Initialization Flowchart (2) (Reception)
465
Figure 16.13 Sample SCIF Initialization Flowchart (3) (Simultaneous Transmission and Reception)
466
Figure 16.14 Sample Serial Transmission Flowchart (1) (First Transmission after Initialization)
467
Figure 16.14 Sample Serial Transmission Flowchart (2) (Second and Subsequent Transmission)
467
Figure 16.15 Sample Serial Reception Flowchart (1) (First Reception after Initialization)
468
Figure 16.15 Sample Serial Reception Flowchart (2) (Second and Subsequent Reception)
469
Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (2) (Second and Subsequent Transfer)
470
Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (1) (First Transfer after Initialization)
471
SCIF Interrupt Sources and DMAC
472
Table 16.4 SCIF Interrupt Sources
473
Notes on Usage
474
Section 17 Infrared Data Association Module (Irda)
477
Features
477
Figure 17.1 Block Diagram of Irda
477
Input/Output Pins
478
Register Description
478
Irda Mode Register (Scsmr_Ir)
478
Table 17.1 Pin Configuration
478
Operation
480
Overview
480
Transmitting
480
Receiving
481
Data Format Specification
481
Figure 17.2 Transmit/Receive Operation
481
Section 18 USB Function Module
483
Features
483
Figure 18.1 Block Diagram of USB
484
Input/Output Pins
485
Table 18.1 Pin Configuration
485
Register Descriptions
486
Interrupt Flag Register 0 (IFR0)
487
Interrupt Flag Register 1 (IFR1)
488
Interrupt Select Register 0 (ISR0)
489
Interrupt Select Register 1 (ISR1)
489
Interrupt Enable Register 0 (IER0)
490
Interrupt Enable Register 1 (IER1)
490
Ep0I Data Register (Epdr0I)
491
Ep0O Data Register (Epdr0O)
491
Ep0S Data Register (Epdr0S)
491
EP1 Data Register (EPDR1)
492
EP2 Data Register (EPDR2)
492
EP3 Data Register (EPDR3)
492
Ep0O Receive Data Size Register (Epsz0O)
493
EP1 Receive Data Size Register (EPSZ1)
493
Trigger Register (TRG)
494
Data Status Register (DASTS)
495
FIFO Clear Register (FCLR)
495
DMA Transfer Setting Register (DMAR)
496
Endpoint Stall Register (EPSTL)
499
Transceiver Control Register (XVERCR)
499
Operation
500
Cable Connection
500
Figure 18.2 Cable Connection Operation
500
Cable Disconnection
501
Control Transfer
501
Figure 18.3 Cable Disconnection Operation
501
Figure 18.4 Transfer Stages in Control Transfer
501
Figure 18.5 Setup Stage Operation
502
Figure 18.6 Data Stage (Control-In) Operation
503
Figure 18.7 Data Stage (Control-Out) Operation
504
Figure 18.8 Status Stage (Control-In) Operation
505
Figure 18.9 Status Stage (Control-Out) Operation
506
EP1 Bulk-Out Transfer (Dual Fifos)
507
Figure 18.10 EP1 Bulk-Out Transfer Operation
507
EP2 Bulk-In Transfer (Dual Fifos)
508
Figure 18.11 EP2 Bulk-In Transfer Operation
508
EP3 Interrupt-In Transfer
509
Figure 18.12 Operation of EP3 Interrupt-In Transfer
509
Processing of USB Standard Commands and Class/Vendor Commands
510
Processing of Commands Transmitted by Control Transfer
510
Table 18.2 Command Decoding on Application Side
510
Stall Operations
511
Overview
511
Forcible Stall by Application
511
Figure 18.13 Forcible Stall by Application
512
Automatic Stall by USB Function Module
513
Figure 18.14 Automatic Stall by USB Function Module
513
DMA Transfer
514
Overview
514
DMA Transfer for Endpoint 1
514
Figure 18.15 RDFN Bit Operation for EP1
514
DMA Transfer for Endpoint 2
515
Figure 18.16 PKTE Bit Operation for EP2
515
Example of USB External Circuitry
516
Figure 18.17 Example of USB Function Module External Circuitry (Internal Transceiver)
517
Figure 18.18 Example of USB Function Module External Circuitry (External Transceiver)
518
Usage Notes
519
Receiving Setup Data
519
Clearing the FIFO
519
Overreading and Overwriting the Data Registers
519
Assigning Interrupt Sources to EP0
520
Clearing the FIFO When DMA Transfer Is Enabled
520
Notes on TR Interrupt
520
Figure 18.19 TR Interrupt Flag Set Timing
520
Section 19 Pin Function Controller
521
Overview
521
Table 19.1 Multiplex Pins
521
Register Descriptions
525
Port a Control Register (PACR)
526
Port B Control Register (PBCR)
527
Port C Control Register (PCCR)
529
Port D Control Register (PDCR)
531
Port E Control Register (PECR)
533
Port E Control Register 2 (PECR2)
534
Port F Control Register (PFCR)
535
Port F Control Register 2 (PFCR2)
536
Port G Control Register
537
Port H Control Register (PHCR)
539
Port J Control Register (PJCR)
540
Port K Control Register (PKCR)
542
Port L Control Register (PLCR)
544
Port M Control Register (PMCR)
545
Port N Control Register (PNCR)
546
Port N Control Register 2 (PNCR2)
548
Port SC Control Register (SCPCR)
549
Section 20 I/O Ports
553
Port a
553
Register Description
553
Figure 20.1 Port a
553
Port a Data Register (PADR)
554
Port B
554
Figure 20.2 Port B
554
Table 20.1 Port a Data Register (PADR) Read/Write Operations
554
Register Description
555
Port B Data Register (PBDR)
555
Table 20.2 Port B Data Register (PBDR) Read/Write Operations
555
Port C
556
Register Description
556
Port C Data Register (PCDR)
556
Figure 20.3 Port C
556
Port D
557
Register Description
557
Port D Data Register (PDDR)
557
Figure 20.4 Port D
557
Table 20.3 Port C Data Register (PCDR) Read/Write Operations
557
Table 20.4 Port D Data Register (PDDR) Read/Write Operations
558
Port E
559
Register Description
559
Port E Data Register (PEDR)
559
Figure 20.5 Port E
559
Port F
560
Register Description
560
Port F Data Register (PFDR)
560
Figure 20.6 Port F
560
Table 20.5 Port E Data Register (PEDR) Read/Write Operations
560
Port G
561
Register Description
561
Figure 20.7 Port G
561
Table 20.6 Port F Data Register (PFDR) Read/Write Operations
561
Port G Data Register
562
Port H
562
Figure 20.8 Port H
562
Table 20.7 Port G Data Register (PGDR) Read/Write Operations
562
Register Description
563
Port H Data Register (PHDR)
563
Table 20.8 Port H Data Register (PHDR) Read/Write Operations
563
Port J
564
Register Description
564
Port J Data Register (PJDR)
564
Figure 20.9 Port J
564
Port K
565
20.10.1 Register Description
565
Port K Data Register (PKDR)
565
Figure 20.10 Port K
565
Table 20.9 Port J Data Register (PJDR) Read/Write Operations
565
Port L
566
20.11.1 Register Description
566
Figure 20.11 Port L
566
Table 20.10 Port K Data Register (PKDR) Read/Write Operations
566
Port L Data Register (PLDR)
567
Port M
567
Figure 20.12 Port M
567
Table 20.11 Port L Data Register (PLDR) Read/Write Operation
567
20.12.1 Register Description
568
Port M Data Register (PMDR)
568
Table 20.12 Port M Data Register (PMDR) Read/Write Operations
568
Port N
569
20.13.1 Register Description
569
Port N Data Register (PNDR)
569
Figure 20.13 Port N
569
SC Port
570
Figure 20.14 SC Port
570
Table 20.13 Port N Data Register (PNDR) Read/Write Operations
570
20.14.1 Register Description
571
Port SC Data Register (SCPDR)
571
Table 20.14 SC Port Data Register (SCPDR) Read/Write Operations
571
Section 21 A/D Converter
573
Features
573
Figure 21.1 Block Diagram of A/D Converter
574
Input/Output Pins
575
Register Descriptions
575
Table 21.1 Pin Configuration
575
A/D Data Registers a to D (ADDRA to ADDRD)
576
A/D Control/Status Registers (ADCSR)
576
Table 21.2 Analog Input Channels and A/D Data Registers
576
Operation
579
Single Mode
579
Multi Mode
579
Scan Mode
580
Input Sampling and A/D Conversion Time
580
Figure 21.2 A/D Conversion Timing
581
Table 21.3 A/D Conversion Time (Single Mode)
581
Table 21.4 A/D Conversion Time (Multi Mode and Scan Mode)
581
Interrupts and DMAC Transfer Request
582
Definitions of A/D Conversion Accuracy
582
Table 21.5 A/D Converter Interrupt Source
582
Figure 21.3 Definitions of A/D Conversion Accuracy
583
Figure 21.4 Definitions of A/D Conversion Accuracy
583
Usage Notes
584
Allowable Signal-Source Impedance
584
Influence to Absolute Accuracy
584
Setting Analog Input Voltage
584
Figure 21.5 Analog Input Circuit Example
584
Notes on Board Design
585
Notes on Countermeasures to Noise
585
Figure 21.6 Example of Analog Input Protection Circuit
585
Figure 21.7 Analog Input Pin Equivalent Circuit
586
Table 21.6 Analog Input Pin Ratings
586
Section 22 User Break Controller
587
Features
587
Figure 22.1 Block Diagram of User Break Controller
588
Register Descriptions
589
Break Address Register a (BARA)
589
Break Address Mask Register a (BAMRA)
590
Break Bus Cycle Register a (BBRA)
590
Break Address Register B (BARB)
591
Break Address Mask Register B (BAMRB)
592
Break Data Register B (BDRB)
592
Break Data Mask Register B (BDMRB)
593
Break Bus Cycle Register B (BBRB)
593
Break Control Register (BRCR)
595
Execution Times Break Register (BETR)
598
DMULS.L Rm,Rn
598
Branch Source Register (BRSR)
599
Branch Destination Register (BRDR)
600
Break ASID Register a (BASRA)
600
Break ASID Register B (BASRB)
601
Operation
601
Flow of the User Break Operation
601
Break on Instruction Fetch Cycle
603
Break on Data Access Cycle
604
Table 22.1 Data Access Cycle Addresses and Operand Size Comparison Conditions
604
Sequential Break
605
Value of Saved Program Counter
605
PC Trace
607
Usage Examples
608
Notes
612
Section 23 User Debugging Interface (UDI)
613
Features
613
Figure 23.1 Block Diagram of UDI
613
Input/Output Pins
614
Table 23.1 Pin Configuration
614
Register Descriptions
615
Bypass Register (SDBPR)
615
Instruction Register (SDIR)
615
Boundary Scan Register (SDBSR)
616
Table 23.2 UDI Commands
616
Table 23.3 SH7705 Pins and Boundary Scan Register Bits
617
ID Register (SDID)
623
Operation
624
TAP Controller
624
Figure 23.2 TAP Controller State Transitions
624
Reset Configuration
625
TDO Output Timing
625
Table 23.4 Reset Configuration
625
UDI Reset
626
UDI Interrupt
626
Figure 23.3 UDI Data Transfer Timing
626
Figure 23.4 UDI Reset
626
Boundary Scan
627
Supported Instructions
627
Points for Attention
628
Usage Notes
629
Advanced User Debugger (AUD)
629
Section 24 List of Registers
631
Register Addresses
632
(By Functional Module, in Order of the Corresponding Section Numbers)
632
Register Bits
641
Register States in each Operating Mode
660
Section 25 Electrical Characteristics
669
Absolute Maximum Ratings
669
Table 25.1 Absolute Maximum Ratings
669
Figure 25.1 Power On/Off Sequence
670
DC Characteristics
671
Table 25.2 DC Characteristics (1) [Common Items]
671
Table 25.2 DC Characteristics (2-A) [Excluding USB-Related Pins]
673
Table 25.2 DC Characteristics (2-B) [USB-Related Pins*]
674
Table 25.2 DC Characteristics (2-C) [USB Transceiver-Related Pins* 1 ]
675
Table 25.3 Permitted Output Current Values
675
AC Characteristics
676
Table 25.4 Maximum Operating Frequencies
676
Clock Timing
677
Table 25.5 Clock Timing
677
Figure 25.2 EXTAL Clock Input Timing
678
Figure 25.3 CKIO Clock Input Timing
678
Figure 25.4 CKIO Clock Output Timing
678
Figure 25.5 Power-On Oscillation Settling Time
679
Figure 25.6 Oscillation Settling Time at Standby Return (Return by Reset)
679
Figure 25.7 Oscillation Settling Time at Standby Return (Return by NMI)
679
Figure 25.8 Oscillation Settling Time at Standby Return
680
Figure 25.9 PLL Synchronization Settling Time by Reset or NMI
680
Figure 25.10 PLL Synchronization Settling Time by IRQ/IRL, PINT Interrupts
681
Figure 25.11 PLL Synchronization Settling Time When Frequency Multiplication
681
Control Signal Timing
682
Table 25.6 Control Signal Timing
682
Figure 25.12 Reset Input Timing
683
Figure 25.13 Interrupt Signal Input Timing
683
Figure 25.14 Bus Release Timing
683
AC Bus Timing
684
Figure 25.15 Pin Drive Timing at Standby
684
Table 25.7 Bus Timing (1)
684
Basic Timing
686
Figure 25.16 Basic Bus Cycle (no Wait)
686
Figure 25.17 Basic Bus Cycle (One Software Wait)
687
Figure 25.18 Basic Bus Cycle (One External Wait)
688
Figure 25.19 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM Bit = 0)
689
Figure 25.20 Address/Data Multiplex I/O Bus Cycle (Three Address Cycles, One Software Wait, One External Wait)
690
Burst ROM Timing
691
Figure 25.21 Burst ROM Read Cycle (One Access Wait, One External Wait, One Burst Wait, Two Bursts)
691
Synchronous DRAM Timing
692
Figure 25.22 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 1 Cycle)
692
Figure 25.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 2 Cycle)
693
Figure 25.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4), (Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 2 Cycle)
694
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4), (Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 1 Cycle)
695
Figure 25.26 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 2 Cycle)
696
Figure 25.27 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRCD = 3 Cycle, TRWL = 2 Cycle)
697
Figure 25.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
698
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
699
Figure 25.30 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
700
Figure 25.36 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle)
706
Figure 25.37 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle)
707
Figure 25.38 Synchronous DRAM Mode Register Write Timing (TRP = 2 Cycle)
708
Table 25.8 Bus Timing (2)
709
Figure 25.39 Access Timing in Low-Frequency Mode (Auto Precharge)
710
Figure 25.40 Synchronous DRAM Auto-Refresh Timing (TRP = 2 Cycle, Low-Frequency Mode)
711
Figure 25.41 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle, Low-Frequency Mode)
712
Figure 25.42 Synchronous DRAM Mode Register Write Timing (TRP = 2 Cycle, Low-Frequency Mode)
713
DMAC Signal Timing
714
Figure
714
Figure 25.43 DREQ Input Timing
714
Figure 25.44 DACK, TEND Output Timing
714
Table 25.9 DMAC Signal Timing
714
TMU Signal Timing
715
Figure
715
Figure 25.45 TCLK Input Timing
715
Figure 25.46 TCLK Clock Input Timing
715
Table 25.10 TMU Signal Timing
715
RTC Signal Timing
716
16-Bit Timer Pulse Unit (TPU) Signal Timing
716
Figure
716
Figure 25.47 Oscillation Settling Time When RTC Crystal Oscillator Is Turned on
716
Figure 25.48 TPU Output Timing
716
Table 25.11 RTC Signal Timing
716
Table 25.12 16-Bit Timer Pulse Unit (TPU) Signal Timing
716
SCIF Module Signal Timing
717
Figure 25.49 SCK Input Clock Timing
717
Table 25.13 SCIF Module Signal Timing
717
USB Module Signal Timing
718
Figure 25.50 SCIF Input/Output Timing in Clock Synchronous Mode
718
Figure 25.51 USB Clock Timing
718
Table 25.14 USB Module Clock Timing
718
USB Transceiver Timing
719
Figure 25.52 Oscillation Settling Time When USB Crystal Oscillator Is Turned on
719
Table 25.15 USB Transceiver Timing
719
Port Input/Output Timing
720
Figure 25.53 I/O Port Timing
720
Table 25.16 Port Input/Output Timing
720
UDI Related Pin Timing
721
Figure 25.54 TCK Input Timing
721
Table 25.17 UDI Related Pin Timing
721
Figure 25.55
722
T R S T Input Timing (Reset Hold)
722
Figure 25.56 UDI Data Transfer Timing
722
A S E M D 0
722
Input Timing
722
Figure 25.58 Output Load Circuit
723
Table 25.18 A/D Converter Characteristics
724
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