NEC mPD75512 Datasheet page 50

Mos integrated circuit 4-bit single-chip microcomputer
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(2)
Serial Transfer Operation
(a)
Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)
Parameter
SCK Cycle Time
SCK High-, Low-Level
Widths
SI Set-Up Time (vs. SCK ↑)
SI Hold Time (vs. SCK ↑ ) t
SCK ↓→ SO Output
Delay Time
*: R
and C
are load resistance and load capacitance of the SO output line.
L
L
(b)
Two-Line and Three-Line Serial I/O Modes (SCK: external clock input)
Parameter
SCK Cycle Time
SCK High-, Low-Level
Widths
SI Set-Up Time (vs. SCK ↑)
SI Hold Time (vs. SCK ↑)
SCK ↓→ SO Output
Delay Time
*: R
and C
are load resistance and load capacitance of the SO output line.
L
L
50
Symbol
Conditions
t
V
= 4.5 to 6.0 V
KCY1
DD
t
V
= 4.5 to 6.0 V
KL1
DD
t
KH1
t
SIK1
KSI1
t
R
= 1 kΩ,
KSO1
L
C
= 100 pF*
L
Symbol
Conditions
t
V
= 4.5 to 6.0 V
KCY2
DD
t
V
= 4.5 to 6.0 V
KL2
DD
t
KH2
t
SIK2
t
KSI2
t
R
= 1 kΩ, C
= 100 pF* V
KSO2
L
L
MIN.
1600
3800
(t
/2)-50
KCY1
(t
/2)-150
KCY1
150
400
V
= 4.5 to 6.0 V
DD
MIN.
800
3200
400
1600
100
400
= 4.5 to 6.0 V
DD
µ PD75512
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
250
ns
1000
ns
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
300
ns
1000
ns

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