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LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(T
= –40 to +85°C)
a
Parameter
Data Retention Supply
Voltage
Data Retention Supply
1
Current*
Release Signal Set Time
Oscillation Stabilization
2
Wait Time*
*1: Does not include current flowing through internal pull-up resistor
2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent
unstable operation when oscillation is started.
3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3
BTM2
BTM1
–
0
0
–
0
1
–
1
0
–
1
1
DATA RETENTION TIMING (releasing STOP mode by RESET)
V
DD
STOP instruction
execution
RESET
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
56
Symbol
Conditions
V
DDDR
I
V
= 2.0 V
DDDR
DDDR
t
SREL
t
Released by RESET
WAIT
Released by interrupt
BTM0
WAIT time ( ): f
= 4.19 MHz
X
20
0
2
/f
(approx. 250 ms)
X
17
1
2
/f
(approx. 31.3 ms)
X
15
1
2
/f
(approx. 7.82 ms)
X
13
1
2
/f
(approx. 1.95 ms)
X
STOP mode
Data retention mode
V
DDDR
STOP mode
Data retention mode
V
DDDR
µ PD75512
MIN.
TYP.
MAX.
Unit
2.0
6.0
V
µ A
0.1
10
µ s
0
17
2
/f
ms
X
*3
ms
Internal reset operation
HALT mode
Operation
mode
t
SREL
t
WAIT
HALT mode
Operation
mode
t
SREL
t
WAIT
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