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P03/SI/SB1
P02/SO/SB0
P01/SCK0
P01
output
latch
Internal bus
8/4
Bit
test
8
8
CSIM0
Fig. 6-8 Serial Interface (Channel 0) Block Diagram
8
Bit manipulation
Slave address register
(8)
(SVA)
Coincidence
RELT
signal
Address comparator
CMDT
(8)
SO0 latch
SET CLR
D
Q
Shift register (SIO0)
(8)
RELD
Bus release/
CMDD
command/
acknowledge
ACKD
detector
circuit
INTCSI0
Serial clock
control
counter
circuit
Serial clock
control
circuit
Bit test
SBIC
Busy/
acknowledge
output
circuit
INTCSI0
)
(
IRQCSI0
set signal
3
f
/2
X
4
f
/2
X
6
f
/2
MPX
X
TOUT F/F
(from timer/
event counter)
External SCK0
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