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(c)
SBI Mode (SCK: internal clock output (master))
Parameter
Symbol
SCK Cycle Time
t
SCK High-, Low-Level
t
Widths
t
SB0, 1 Set-Up Time
t
(vs. SCK ↑ )
SB0, 1 Hold Time
t
(vs. SCK ↑ )
SCK ↓→ SB0, 1 Output
t
Delay Time
SCK ↑→ SB0, 1 ↓
t
SB0,1 ↓→ SCK
t
SB0, 1 Low-Level Width
t
SB0, 1 High-Level Width
t
*: R
and C
are load resistance and load capacitance of the SO output line.
L
L
(d)
SBI Mode (SCK: external clock input (slave))
Parameter
Symbol
SCK Cycle Time
t
SCK High-, Low-Level
t
Widths
t
SB0, 1 Set-Up Time
t
(vs. SCK ↑ )
SB0, 1 Hold Time
t
(vs. SCK ↑ )
SCK ↓→ SB0, 1 Output
t
Delay Time
SCK ↑→ SB0, 1 ↓
t
SB0,1 ↓→ SCK ↓
t
SB0, 1 Low-Level Width
t
SB0, 1 High-Level Width
t
*: R
and C
are load resistance and load capacitance of the SO output line.
L
L
Conditions
V
= 4.5 to 6.0 V
KCY3
DD
V
= 4.5 to 6.0 V
KL3
DD
KH3
SIK3
KSI3
R
= 1 kΩ,
KSO3
L
C
= 100 pF*
L
KSB
SBK
SBL
SBH
Conditions
V
= 4.5 to 6.0 V
KCY4
DD
V
= 4.5 to 6.0 V
KL4
DD
KH4
SIK4
KSI4
R
= 1 kΩ,
KSO4
L
C
= 100 pF*
L
KSB
SBK
SBL
SBH
MIN.
1600
3800
t
/2-50
KCY3
t
/2-150
KCY3
150
t
/2
KCY3
V
= 4.5 to 6.0 V
0
DD
0
t
KCY3
t
KCY3
t
KCY3
t
KCY3
MIN.
800
3200
400
1600
100
t
/2
KCY4
V
= 4.5 to 6.0 V
0
DD
0
t
KCY4
t
KCY4
t
KCY4
t
KCY4
µ PD75512
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
250
ns
1000
ns
ns
ns
ns
ns
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
300
ns
1000
ns
ns
ns
ns
ns
51
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