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Instruc-
Mne-
Operand
tions
monics
Subrou-
CALL
!addr
tine/
Stack
Control
CALLF
!faddr
RET
RETS
RETI
PUSH
rp
BS
POP
rp
BS
Inter-
EI
rupt
IExxx
Control
DI
IExxx
I/O
IN
*
1
A,PORTn
XA,PORTn
OUT *
1
PORTn,A
PORTn,XA
CPU
HALT
Control
STOP
NOP
Special
RBn
SEL
MBn
GETI *
2
taddr
*1: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.
*2: The TBR, and TCALL instructions are the assembler pseudo-instructions for the table definition of
GETI instruction.
Ma-
chine
Bytes
Operation
Cyc-
les
(SP-4)(SP-1)(SP-2) ← PC
3
3
(SP-3) ← MBE, RBE, PC
← addr, SP ← SP-4
PC
13-0
(SP-4)(SP-1)(SP-2) ← PC
2
2
(SP-3) ← MBE, RBE, PC
← 00, faddr, SP ← SP-4
PC
13-0
1
3
MBE, RBE, PC
13,12
← (SP)(SP+3)(SP+2)
PC
11-0
SP ← SP+4
1
3+S
MBE, RBE, PC
13,12
← (SP)(SP+3)(SP+2)
PC
11-0
SP ← SP+4, then skip unconditionally
← (SP+1)
1
3
PC
13,12
← (SP)(SP+3)(SP+2)
PC
11-0
PSW ← (SP+4)(SP+5), SP ← SP+6
(SP-1)(SP-2) ← rp, SP ← SP-2
1
1
(SP-1) ← MBS, (SP-2) ← RBS, SP ← SP-2
2
2
rp ← (SP+1)(SP), SP ← SP+2
1
1
MBS ← (SP+1), RBS ← (SP), SP ← SP+2
2
2
IME (IPS.3) ← 1
2
2
IExxx ← 1
2
2
IME (IPS.3) ← 0
2
2
IExxx ← 0
2
2
A ← PORT
2
2
n
XA ← PORT
2
2
,PORT
n+1
← A
2
2
PORT
n
2
2
PORT
,PORT
n+1
n
Set HALT Mode (PCC.2 ← 1)
2
2
Set STOP Mode (PCC.3 ← 1)
2
2
1
1
No Operation
RBS ← n (n = 0-3)
2
2
MBS ← n (n = 0, 1, 15)
2
2
. Where TBR instruction,
1
3
← (taddr)
PC
13-0
.........................................................
. Where TCALL instruction,
(SP-4)(SP-1)(SP-2) ← PC
(SP-3) ← MBE, RBE, PC
← (taddr)
PC
13-0
SP ← SP-4
.........................................................
. Except for TBR and TCALL
instructions,
Instruction execution of
(taddr)(taddr+1)
Ad-
dress-
ing
Area
*6
11-0
13,12
*9
11-0
13,12
← (SP+1)
← (SP+1)
(n = 0-15)
n
(n = 4, 6)
(n = 2-7, 9-14)
← XA
(n = 4, 6)
*10
+(taddr+1)
4-0
11-0
13,12
+(taddr+1)
5-0
µ PD75512
Skip
Conditions
Undefined
.............................
.............................
Depends on
referenced
instruction
43
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