Pcm Timing Information - Laird BT800 series Hardware Integration Manual

BT800 Hardware Integration Guide
Version 0.2
13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats.

A sample rate of 8ksps.

Little or big endian bit order.

For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros

or a programmable 3-bit audio attenuation compatible with some codecs.
Figure 8: 16-bit Slot Length and Sample Formats
9.7

PCM Timing Information

Table 9: PCM Timing information.
Parameter
Symbol
mclk
f PCM_CLK frequency
PCM_SYNC frequency for SCO connection
-
mclkh
t
PCM_CLK high
(a)
mclkl PCM_CLK low
t a)
PCM_CLK jitter
-
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4MHz DDS generation.
Frequency selection is
programmable.
48MHz DDS generation.
Frequency selection is
programmable.
4MHz DDS generation
4MHz DDS generation
48MHz DDS generation
18
Min Typ Max
128
- 256 -
512
2.9 - -
- 8 -
980 - -
730 - -
- - 21
CONN-GUIDE-BT800_v0_2
Unit
kHz
kHz
kHz
ns
ns
ns
pk-p