Keithley KPCI-PIO32IOA User Manual page 62

B-6 I/O Address Mapping
3. Prior to sending data, a user circuit sets INT_ENN to logic low. Board firmware detects that
INT_ENN is low and allows the edges of interrupt signals at INT_REQ to be detected.
4. When data is ready to be transferred and processed, the user circuit sends an external inter-
rupt request signal to INT_REQ.
5. Board firmware detects the rising or falling edge of the INT_REQ signal, depending on
interrupt polarity settings in the port-group control registers
6. Software sets bit 6 of the interrupt control/status register high or low depending on whether
the user wants a PCI interrupt to be triggered by the falling or rising edge of INT_REQ.
7. If inputs are configured to latch, the current data value will be latched. (See bits 5 and 6 in
Table B-2.)
8. The interrupt-received status in board firmware causes interrupt-pending bit 17 of the inter-
rupt control/status register to be set to logic high.
9. The interrupt-received status in board firmware causes a computer CPU interrupt to start,
stopping execution of the current CPU task.
10. Computer hardware detects an interrupt request signal and transfers control to an interrupt
service routine (ISR).
11. Computer software starts the ISR, which takes control of the CPU and starts processing the
KPCI-PIO32IOA or KPCI-PDISO8A input data.
12. The ISR proceeds.
13. Ideally, for a well-planned data acquisition session, the conditions are met while the ISR is in
progress, and the interrupt-pending bit is set. No new external interrupt requests occur during
this time.
However if the above conditions are not met while the interrupt-pending bit is set, the fol-
lowing occurs:
a. The rising or falling edges of interrupt signals have no effect; these interrupts are missed.
b. When the first rising or falling edge is missed, the problem is recorded as follows:
1. Board firmware detects the missed interrupt, causing interrupt-missed bit 23 of the
interrupt control/status register to be set to logic high.
2. Computer software, if appropriately programmed, detects that bit 23 has been set and
notifies the user of the missed interrupt.
c. If additional rising or falling edges are missed (edges 2, 3, ...., n), the problems are not
recorded, as follows:
1. No additional interrupt-missed bits are set (there is only one interrupt-missed bit).
2. Computer software cannot further notify the user.
14. The ISR, if appropriately programmed, writes ones (Acknowledge) to clear the interrupt-
pending bit 17 and interrupt-missed bit 23 in the interrupt control/status register to logic low,
which clears interrupt-pending status and interrupt-missing status in board firmware.
15. The ISR, if appropriately programmed, clears the rising/falling edge of bit 6 in the interrupt
control/status register to logic low.
16. The ISR finishes.
17. The ISR dispatcher of the operating system detects that the ISR has finished and sends an
end-of-interrupt instruction to the CPU.
NOTE The end-of-ISR behavior depends on the operating system being used.
18. The CPU returns to the task that it was executing at the time of the interrupt.
19. At some point, the user circuit may disable interrupts and latching by setting INT_ENN to
logic high.
20. Board firmware detects that INT_ENN is high and rejects interrupt signals at INT_REQ.
KPCI-PIO32IOA and KPCI-PDISO8A User's Manual
(Table B-2).