Keithley KPCI-PIO32IOA User Manual page 55

Board Address Mapping
Offset (byte)
BADDRx 0
1
2
3
4
5
6
7
...
34 - 37
38 - 3A
3B
BADDRx + 0x03
Control Byte Format:
-- Bit 7 - This bit to be ignored.
-- Bit 6 - Access Mode Select – For B5 and B6 see table below.
-- Bit 5 - Access Mode Select – For B5 and B6 see table below.
-- Bit 4:0 - These bits to be ignored.
B6 B5 (Control byte)
0 0 – No input latching on rising interrupt edge.
0 1 – Latch group inputs on rising interrupt edge.
1 0 – No input latching on falling interrupt edge.
1 1 – Latch group inputs on falling interrupt edge.
BADDRx + 0x38
Interrupt Status Register Format: (DWord Access)
(Taken from the AMCC Architecture – used on KPCI-PIOs and KPCI-3160)
--Bit 23 – Interrupt missed =1 for missed interrupt. Write 1 to acknowledge/clear.
--Bit 22:18 – These bits to be ignored.
--Bit 17 – Interrupt pending = 1 for pending interrupt. Write 1 to acknowledge/clear.
--Bit 16 – This bit to be ignored.
---------------
--Bit 15:13 – These bits to be ignored.
--Bit 12 – Interrupt enable = 1, HW Interrupts enabled, 0 = HW Interrupts disabled.
--Bit 11:08 – These bits to be ignored.
---------------
--Bit 7 – This bit to be ignored.
--Bit 6 – Interrupt polarity select = 1 for falling edge, Write 0 for rising edge.
--Bit 5:0 – These bits to be ignored.
(x = 0 or 1) IO mapped use BADDR0. Memory mapped use BADDR1.
Content Description
Port A Read Only – Input Register
Port B Read Only
NA
Control Latching control (R/W)
Port A' Readback / Write – Output Register
Port B' Readback / Write (KPCI-PIO32IOA Only)
NA
NA
FW Rev ASCII format: "A0xx" (Read Only)
INT CSR Interrupt Control Register (R/W)
NA
(KPCI-PIO32IOA Only)
HW 2/27/02
Rev B
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