ATA C
B
OMMAND
LOCK AND
Idle — 97h, E3h
When issued by the host, the device's internal controller sets the BSY bit,
enters the Idle mode, clears the BSY bit, and generates an interrupt. If the
sector count is non-zero, it is interpreted as a timer count with each count
being 5ms, and the automatic power-down mode is enabled. If the sector
count is zero, the automatic power-down mode is disabled.
Register
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive Head
Command
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
3150C-10DSR
S
D
ET
ESCRIPTION
Table 53: Idle — 97h, E3h
D
D
7
6
Timer Count (5ms increments)
X
X
S
S
ILICON
YSTEMS
All unauthorized use and/or reproduction is prohibited.
P
67
AGE
SSD-C
XXX
D
D
D
5
4
3
X
X
X
X
X
Drive
97h or E3h
P
ROPRIETARY
(I)-3150 D
S
ATA
HEET
D
D
D
2
1
0
X
F
2, 2009
EBRUARY
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