1. Manuals
  2. Brands
  3. Silicon Systems Manuals
  4. Storage
  5. SILICONDRIVE II SSD-D32G(I)-4300
  6. Datasheet

Silicon Systems SILICONDRIVE II SSD-D32G(I)-4300 Datasheet

2.5" pata drive
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
O
VERVIEW
The SiliconDrive II 2.5" PATA Drive is an
optimal time-to-market replacement for
hard drives and flash cards or in host
systems that require low power and
scalable storage solutions.
SiliconDrive II technology is engineered
exclusively for the high performance, high
reliability and multi-year product lifecycle
requirements of the Enterprise System
OEM
market.
applications include broadband data and
voice networks, military systems, flight
system
avionics,
industrial
control
surveillance, storage networking, VoIP,
wireless infrastructure, and interactive
kiosks.
Every SiliconDrive II 2.5" PATA Drive is
integrated with SiliconSystems patented
PowerArmor
and
SiSMART and SiSecure technologies.
PowerArmor prevents data corruption and
loss
from
power
integrating patented technology into every
SiliconDrive II.
SiSMART acts as an early warning system
to eliminate unscheduled downtime by
constantly monitoring and reporting the
exact amount of remaining storage system
useful life.
SiSecure is a comprehensive suite of
user-selectable security technologies that
solves the critical need for robust storage
security
for
embedded
applications that have a small footprint
and low-power requirement.
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
26840 A
V
P
, A
LISO
IEJO
ARKWAY
4300D-00DSR
S
Typical
end-market
medical
equipment,
systems,
video
patent-pending
disturbances
systems
S
S
ILICON
YSTEMS
All unauthorized use and/or reproduction is prohibited.
•
V
, CA 92656
P
LISO
IEJO
HONE
D
D
ILICON
RIVE
S
S
I
ECURE
SiZone
Data zones with different
security parameters.
SiKey
Ties SiliconDrive to a specific
host and/or software IP.
SiProtect Protection software for
password-required, read/write,
or read-only access.
SiSweep Ultra-fast data erasure.
SiPurge
Non-recoverable data erasure.
AutoLock Automatically locks the
SiliconDrive.
F
EATURES
• RoHS 6 of 6 compliant
• Integrated PowerArmor, SiSMART, and
SiSecure technology
• Capacity range: 4GB to 32GB
• MTBF 4,000,000 hours
by
32GB PATA
SSD-D32G(I)-4300
Click here
P
ROPRIETARY
•
: 949.900.9400
F
: 949.900.9500
AX
S
ATA
HEET
II 2.5" PATA D
SSD-D
(I)-4300
XXX
Click here
•
http://www.siliconsystems.com
F
EBRUARY
RIVE
27, 2009

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SILICONDRIVE II SSD-D32G(I)-4300 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Silicon Systems SILICONDRIVE II SSD-D32G(I)-4300

Summary of Contents for Silicon Systems SILICONDRIVE II SSD-D32G(I)-4300

  • Page 1 VERVIEW The SiliconDrive II 2.5" PATA Drive is an optimal time-to-market replacement for hard drives and flash cards or in host systems that require low power and scalable storage solutions. SiliconDrive II technology is engineered exclusively for the high performance, high reliability and multi-year product lifecycle requirements of the Enterprise System market.
  • Page 2 EVISION ISTORY EVISION ISTORY Document No. Release Date 4300D-00DSR February 27, 2009 This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 4300D-00DSR Changes Initial release. ILICON YSTEMS ROPRIETARY AGE II SSD-D...

  • Page 3: Table Of Contents

    ABLE OF ONTENTS Overview ... i SiSecure... i Features ... i Revision History... List of Figures ... List of Tables ... Physical Specifications ... 1 Physical Dimensions ... 1 Pin Locations... 2 Jumper Settings ... 2 Product Specifications ... 3 System Performance...
  • Page 4 ABLE OF ONTENTS Task File Register Specification ... 27 ATA Registers... 28 Data Register ... 28 Error Register ... 28 Feature Register... 29 Sector Count Register ... 30 Sector Number Register... 31 Cylinder Low Register ... 32 Cylinder High Register ... 33 Drive/Head Register ...
  • Page 5 ABLE OF ONTENTS Read Sector — 20h, 21h... 56 Read Long Sector(s) — 22h, 23h... 57 Read Verify Sector(s) — 40h, 41h ... 58 Seek — 7Xh ... 59 Set Features — EFh... 60 Set Multiple Mode — C6h ... 61 Set Sleep Mode —...

  • Page 6: List Of Figures

    SSD-D (I)-4300 D IST OF IGURES HEET IST OF IGURES Figure 1: Physical Dimensions... 1 Figure 2: Pin Locations ... 2 Figure 3: Jumper Settings... 2 Figure 4: True IDE PIO Mode Read/Write Access Timing Diagram ... 13 Figure 5: True IDE PIO Multiword DMA Read/Write Access Timing ... 15 Figure 6: Initiating a UDMA Data-In Burst...
  • Page 7 SSD-D (I)-4300 D IST OF ABLES HEET IST OF ABLES Table 1: System Performance ... 3 Table 2: System Power Requirements ... 3 Table 3: Reliability... 4 Table 4: Operational Life Span ... 4 Table 5: Product Capacity Specifications ... 5 Table 6: Environmental Specifications...
  • Page 8 SSD-D (I)-4300 D IST OF ABLES HEET Table 28: ATA Command Set ... 40 Table 29: Check Power Mode — 98h, E5h... 42 Table 30: Executive Drive Diagnostic — 90h... 43 Table 31: Format Track — 50h ... 44 Table 32: Identify Drive — ECh ... 45 Table 33: Identify Drive —...
  • Page 9 SSD-D (I)-4300 D IST OF ABLES HEET Table 57: Request Sense — 03h... 71 Table 58: Extended Error Codes ... 71 Table 59: Translate Sector — 87h ... 72 Table 60: Wear-Level — F5h... 73 Table 61: Write Multiple w/o Erase — CDh ... 74 Table 62: Write Sector(s) w/o Erase —...

  • Page 10: Physical Specifications

    HYSICAL PECIFICATIONS HYSICAL PECIFICATIONS The SiliconDrive II 2.5" PATA Drive products are offered in an industry- standard 2.5" PATA Drive form factor. See details regarding 2.5" PATA Drive capacities. HYSICAL IMENSIONS This section provides diagrams that describe the physical dimensions for the 2.5"...

  • Page 11: Pin Locations

    HYSICAL PECIFICATIONS OCATIONS The following diagram identifies the pin locations of the 2.5" PATA Drive. UMPER ETTINGS The following diagram defines the SiliconDrive II 2.5" PATA Drive jumper settings. This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 12: Product Specifications

    RODUCT PECIFICATIONS RODUCT PECIFICATIONS Note: All SiliconDrive II 2.5" PATA Drive values quoted are typical at 25°C and nominal supply voltage. YSTEM ERFORMANCE Reset to Ready Startup Time (Typical/Maximum) Read Transfer Rate (Typical) Write Transfer Rate (Typical) Burst Transfer Rate Controller Overhead (Command to DRQ) YSTEM OWER...

  • Page 13: Reliability

    RODUCT PECIFICATIONS ELIABILITY MTBF (@ 25ºC) Bit Error Rate ROJECTED PERATIONAL SiliconDrive Part# SSD-D032G-4300 SSD-D016G-4300 SSD-D008G-4300 SSD-D004G-4300 * There are unlimited read cycles. Service life is determined using SiliconSystems’ LifeEST calculation at 100% duty cycle with 25% write cycles. LifeEST is a comprehensive measurement that considers numerous factors to determine the projected life span of a SiliconDrive.

  • Page 14: Product Capacity Specifications

    RODUCT PECIFICATIONS RODUCT APACITY Table 5: Product Capacity Specifications Product Capacity Capacity (Bytes) 4,110,188,544 8,195,604,480 16GB 16,391,208,960 32GB 32,782,417,920 NVIRONMENTAL PECIFICATIONS Temperature Humidity Vibration Shock Altitude This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 15: Electrical Specification

    LECTRICAL PECIFICATION LECTRICAL PECIFICATION SSIGNMENTS The following table describes the SiliconDrive II 2.5" PATA Drive 44-pin IDE connector signals. IDE-ATA RESET# DMARQ IOWR# IORD# IORDY DMACK# INTRQ CS0# DASP# This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 16: Signal Descriptions

    LECTRICAL PECIFICATION IGNAL ESCRIPTIONS Signal Name Pin(s) A2-A0 36, 33, -CS0,-CS1 37, 38 -CSEL D15-D0 18, 16, 14, 12, 10, 8, 6, 4, 3, 5, 7, 9, 11, 13, 15, 17 -DMACK DASP This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 17 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name Pin(s) DMARQ This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 4300D-00DSR Type Description DMA Request. This signal is used for DMA transfers between the host and device.
  • Page 18 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name Pin(s) DMARQ# (UDMA protocol active) 2, 19, 22, 24, 26, 30, 40, INTRQ This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited. 4300D-00DSR Type Description This signal is a DMA request that is used...
  • Page 19 LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name Pin(s) IORDY (True IDE mode) -IORD (True IDE mode) -DDMARDY (UDMA write protocol active) DSTROBE (UDMA read protocol active) -IOWR (True IDE mode) -HDMARDY (UDMA read protocol active) This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 20: Absolute Maximum Ratings

    LECTRICAL PECIFICATION Table 8: Signal Descriptions (Continued) Signal Name Pin(s) HDSTROBE (UDMA write protocol active) STOP (UDMA protocol active) -PDIAG -RESET 41, 42 BSOLUTE AXIMUM Symbol Parameter Storage Temperature Operating Temperature Input Voltage Output Voltage This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 21: Dc Characteristics

    LECTRICAL PECIFICATION DC C HARACTERISTICS Symbol Parameter Input Leakage *(1) Current Output Leakage *(1) Current - Read Current Write Current Standby Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 22: Ac Characteristics

    LECTRICAL PECIFICATION AC C HARACTERISTICS True IDE PIO Mode Read/Write Access Timing ADDR valid (A02, A01, A00, -CS0, -CS1) (See note 1) (See note 1) -IORD / -IOWR Write Data (D15:D00) (See note 2) (See note 2) Read Data (D15:D00) (See note 2) (See note 2) -IOCS16...

  • Page 23: Table 11: True Ide Pio Mode Read/Write Access Timing

    LECTRICAL PECIFICATION Table 11: True IDE PIO Mode Read/Write Access Timing Symbol Item Cycle Time (minimum) Address Valid to IORD/-IOWR Setup (minimum) -IORD/-IOWR (minimum) 165 -IORD/-IOWR (minimum) register (8 bit) -IORD/-IOWR Recovery Time (minimum) -IOWR Data Setup (minimum) -IOWR Data Hold (minimum) -IORD Data Setup (minimum)

  • Page 24: True Ide Pio Multiword Dma Read/Write Access Timing

    LECTRICAL PECIFICATION 3. The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is inactive, then the host waits until IORDY is active before the PIO cycle can be completed. If the Drive is not driving IORDY negated at t after the activation of -IORD or -IOWR, then t and t...

  • Page 25: Table 12: True Ide Pio Multiword Dma Read/Write Access Timing

    LECTRICAL PECIFICATION Table 12: True IDE PIO Multiword DMA Read/Write Access Timing Symbol Item Cycle Time (minimum) 480 -IORD/-IOWR Asserted Width (minimum) -IORD Data Access (maximum) -IORD Data Hold (minimum) -IORD/-IOWR Data Setup (minimum) -IOWR Data Hold (minimum) DMACK to –IORD/- IOWR Setup (minimum) -IORD / -IOWR to -...

  • Page 26: Ultra Dma Data Burst Timing Requirements

    LECTRICAL PECIFICATION Ultra DMA Data Burst Timing Requirements The following figures and table describe the requirements for the Ultra DMA (UDMA) data burst timing. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Figure 6: Initiating a UDMA Data-In Burst Note: The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE, and IORDY:DDMARDY-:DSTROBE signal lines are not in effect until...

  • Page 27: Figure 7: Sustained Udma Data-In Burst

    LECTRICAL PECIFICATION DSTROBE at device DD(15:0) at device DSTROBE at host DD(15:0) at host Note: DD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that the cable settling time as well as cable propagation delay does not allow the data signals to be considered stable at the host until some time after they are driven by the device.

  • Page 28: Figure 9: Device Terminating A Udma Data-In Burst

    LECTRICAL PECIFICATION DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Figure 9: Device Terminating a UDMA Data-In Burst Note: The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE, and IORDY:DDMARDY-:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

  • Page 29: Figure 10: Host Terminating A Udma Data-In Burst

    LECTRICAL PECIFICATION DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Figure 10: Host Terminating a UDMA Data-In Burst Note: The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE, and IORDY:DDMARDY-:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

  • Page 30: Figure 11: Initiating A Udma Data-Out Burst

    LECTRICAL PECIFICATION DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- Figure 11: Initiating a UDMA Data-Out Burst Note: :DSTROBE, and DIOR-:HDMARDY-:HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. HSTROBE at host DD(15:0)

  • Page 31: Figure 13: Device Pausing A Udma Data-Out Burst

    LECTRICAL PECIFICATION DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) Figure 13: Device Pausing a UDMA Data-Out Burst Notes: 1. The device may negate DMARQ to request termination of the UDMA burst no sooner than t 2.

  • Page 32: Figure 14: Host Terminating A Udma Data-Out Burst

    LECTRICAL PECIFICATION DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- Figure 14: Host Terminating a UDMA Data-Out Burst Note: :DSTROBE, and DIOR-:HDMARDY-:HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

  • Page 33: Figure 15: Device Terminating A Udma Data-Out Burst

    LECTRICAL PECIFICATION DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- Figure 15: Device Terminating a UDMA Data-Out Burst Note: :DSTROBE, and DIOR-:HDMARDY-:HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Table 13: UDMA Data Burst Timing Requirements Mode 0 Symbol...
  • Page 34 LECTRICAL PECIFICATION Table 13: UDMA Data Burst Timing Requirements (Continued) Mode 0 Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. IORDYZ ZIORDY This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 35 LECTRICAL PECIFICATION Table 13: UDMA Data Burst Timing Requirements (Continued) Mode 0 Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Notes: 1. Timing parameters are measured at the connector of the sender or receiver to which the parameter applies. Both STROBE and DMARDY- timing measurements are taken at the sender’s connector.

  • Page 36: Ata And True Ide Register Decoding

    IDE R EGISTER IDE R SiliconDrive II can be configured as either a a memory-mapped or an an I/O devices. As noted earlier, communication to and from the drive is accomplished using the ATA Command Block. EGISTER The Task File registers are used for reading and writing the storage data in the SiliconDrive II.

  • Page 37: Ata Registers

    ATA R EGISTERS ATA R EGISTERS EGISTER The Data register is a 16-bit register used to transfer data blocks between the host and drive buffers. The register may set to 8-bit mode by using the Set Features Command defined in RROR EGISTER The Error register contains the error status, if any, generated from the last...

  • Page 38: Feature Register

    ATA R EGISTERS EATURE EGISTER The Feature register is command-specific and used to enable and disable interface features. This register supports only either odd or even byte data transfers. Operation Read/Write This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 39: Sector Count Register

    ATA R EGISTERS ECTOR OUNT EGISTER The Sector Count register is used to read or write the sector count of the data for which an ATA transfer has been made. Operation Read/Write Default Value This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 40: Sector Number Register

    ATA R EGISTERS ECTOR UMBER EGISTER The Sector Number register is set by the host to specify the starting sector number associated with the next ATA command to be executed. Following a qualified ATA command sequence, the device sets the register value to the last sector read or written as a result of the previous AT command.

  • Page 41: Cylinder Low Register

    ATA R EGISTERS YLINDER EGISTER The Cylinder Low register is set by the host to specify the cylinder number low byte. Following an ATA command, the content of the register is written by the device, identifying the cylinder number low byte. In LBA mode, the 8-bit register maintains the contents of the Logical Block number address bits A15:A08.

  • Page 42: Cylinder High Register

    ATA R EGISTERS YLINDER EGISTER The Cylinder High register is set by the host to specify the cylinder number high byte. Following an ATA command, the content of the register is set internally by the device, identifying the cylinder number high byte. In LBA mode, the 8-bit register maintains the contents of the Logical Block number address bits A23:A16.

  • Page 43: Drive/Head Register

    ATA R EGISTERS RIVE EGISTER The Drive/Head register is used by the host and the device to select the type of addressing (CHS or LBA), the drive letter, and either bits 3-0 of the head number in CHS mode or logical block number bits 27-24 in LBA mode. Operation Read/Write Default...

  • Page 44: Status Register

    ATA R EGISTERS TATUS EGISTER The Status register provides the device’s current status to the host. The status register is an 8-bit read-only register. When the contents of the register are read by the host, the IREQ# bit is cleared. Operation Read/Write Default Value...

  • Page 45: Command Register

    ATA R EGISTERS OMMAND EGISTER The Command register specifies the ATA command code being issued to the drive by the host. Execution of the command begins immediately following the issuance of the command register code by the host. Operation Read/Write "All but CU / E / MU / R / SD/MMC+:ATA Command Block and Set Description"...

  • Page 46: Alternate Status Register

    ATA R EGISTERS LTERNATE TATUS The Alternate Status register is a read-only register indicating the status of the device, following the previous ATA command. See for specific details. Operation Read/Write Default Value This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 47: Device Control Register

    ATA R EGISTERS EVICE ONTROL EGISTER The Device Control register is used to control the interrupt request and issue ATA software resets. Operation Write Bit(s) Description Reserved bits. Always set to 1. Software Reset (SRST). When set, resets the ATA software. Interrupt Enable (nIEN).

  • Page 48: Device Address Register

    ATA R EGISTERS EVICE DDRESS EGISTER The Device Address register is used to maintain compatibility with ATA disk drive interfaces. Operation Read/Write Default Value Bit(s) Description Reserved bit. Write Gate (nWTG). Low when a write to the device is in process. nHS3 to nHS0.

  • Page 49: Ata Command Block And Set Description

    ATA C OMMAND LOCK AND ATA C OMMAND LOCK AND In accordance with the ANSI ATA Specification, the device implements seven registers that are used to transfer instructions to the device by the host. These commands follow the ANSI standard ATA protocol. A description of the ATA command block is provided in the following table.
  • Page 50 ATA C OMMAND LOCK AND Table 28: ATA Command Set (Continued) Class Command Name Read Long Sector Read Sector(s) Read Verify Sector(s) 40h, 41h Recalibrate Request Sense Seek Set Features Set Multiple Mode Set Sleep Mode Standby Standby Immediate Translate Sector Wear Level Write Buffer Write DMA*...

  • Page 51: Check Power Mode - 98H, E5H

    ATA C OMMAND LOCK AND Check Power Mode — 98h, E5h The Check Power Mode command verifies the device’s current power mode. When the device is configured for standby mode or is entering or exiting standby, the BSY bit is set, the Sector Count register set to 00h, and the BSY bit is cleared.

  • Page 52: Executive Drive Diagnostic - 90H

    ATA C OMMAND LOCK AND Executive Drive Diagnostic — 90h The Executive Drive Diagnostic performs an internal read write diagnostic test using (AA55h and 55AAh). If an error is detected in the read/write buffer, the Error register reports the appropriate diagnostic code. Table 30: Executive Drive Diagnostic —...

  • Page 53: Format Track - 50H

    ATA C OMMAND LOCK AND Format Track — 50h The Format Track command formats the common solid-state memory array. Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head Command This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 54: Identify Drive - Ech

    ATA C OMMAND LOCK AND Identify Drive — ECh Issued by the host, the Identify Drive command provides 256 bytes of drive attribute data (i.e., sector size, count, and so on) The identify drive data structure is detailed in the following table. Register Feature Sector Count...

  • Page 55: Identify Drive - Drive Attribute Data

    ATA C OMMAND LOCK AND Identify Drive — Drive Attribute Data Table 33: Identify Drive — Drive Attribute Data Word Data Default Address 045Ah XXXXh 0000h 00XXh 0000h XXXXh XXXXh XXXXh 0000h 10-19 XXXXh This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.
  • Page 56 ATA C OMMAND LOCK AND Table 33: Identify Drive — Drive Attribute Data (Continued) Word Data Default Address 0001h 0001h 0004h 23-26 XXXXh 27-46 XXXXh 8001h 0000h 0f00h 0000h 0200h 0000h 0007h XXXXh XXXXh XXXXh 57-58 XXXXh 010Xh 60-61 XXXXh This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
  • Page 57 ATA C OMMAND LOCK AND Table 33: Identify Drive — Drive Attribute Data (Continued) Word Data Default Address 0000h 0007h 0003h 0078h 0078h 0078h 0078h 003Eh 001Fh 0002h This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc. All unauthorized use and/or reproduction is prohibited.

  • Page 58: Idle - 97H, E3H

    ATA C OMMAND LOCK AND Idle — 97h, E3h When issued by the host, the device’s internal controller sets the BSY bit, enters the Idle mode, clears the BSY bit, and generates an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5ms, and the automatic power-down mode is enabled.

  • Page 59: Idle Immediate - 95H, E1H

    ATA C OMMAND LOCK AND Idle Immediate — 95h, E1h When issued by the host, the device’s internal controller sets the BSY bit, enters Idle Mode, clears the BSY bit, and issues an interrupt. The interrupt is issued whether or not the Idle mode is fully entered. Register Feature Sector Count...

  • Page 60: Initialize Drive Parameters - 91H

    ATA C OMMAND LOCK AND Initialize Drive Parameters — 91h Initialize Drive Parameters allows the host to set the sector counts per track and the head counts per cylinder to 1 Fixed. Upon issuance of the command, the device sets the BSY bit and associated parameters, clears the BSY bit, and issues an interrupt.

  • Page 61: Recalibrate - 1Xh

    ATA C OMMAND LOCK AND Recalibrate — 1Xh The Recalibrate command sets the cylinder low and high, head number to 0h, and sector number to 1h in CHS mode. In LBA mode (i.e., LBA = 1), the sector number is set to 0h. Register Feature Sector Count...

  • Page 62: Read Buffer - E4H

    ATA C OMMAND LOCK AND Read Buffer — E4h The Read Buffer command allows the host to read the contents of the sector buffer. When issued, the device sets the BSY bit and sets up the sector buffer data in preparation for the read operation. When the data is ready, the DRQ bit is set and the BSY bit in the Status register are set and cleared, respectively.

  • Page 63: Read Dma - C8H

    ATA C OMMAND LOCK AND Read DMA — C8h The Read DMA command allows the host to read data using the DMA transfer protocol. Note: This function does not apply to SiliconDrive IIs that have DMA disabled. Register Feature Sector Count Sector Number Cylinder Low Cylinder High...

  • Page 64: Read Multiple - C4H

    ATA C OMMAND LOCK AND Read Multiple — C4h The Read Multiple command executes similarly to the Read Sector command, with the exception that interrupts are issued only when a block containing the counts of sectors defined by the Set Multiple command is transferred. Register Feature Sector Count...

  • Page 65: Read Sector - 20H, 21H

    ATA C OMMAND LOCK AND Read Sector — 20h, 21h The Read Sector command allows the host to read sectors 1 to 256 as specified in the Sector Count register. If the sector count is set to 0h, all 256 sectors of data are made available.

  • Page 66: Read Long Sector(S) - 22H, 23H

    ATA C OMMAND LOCK AND Read Long Sector(s) — 22h, 23h The Read Long Sector(s) command operates similarly to the Read Sector(s) command, with the exception that it transfers requested data sectors and ECC data. The long instruction ECC byte transfer for Long commands is a byte transfer at a fixed length of 4 bytes.

  • Page 67: Read Verify Sector(S) - 40H, 41H

    ATA C OMMAND LOCK AND Read Verify Sector(s) — 40h, 41h The Read Verify Sector(s) command operates similarly to the Read Sector(s) command, with the exception that is does not set the DRQ bit and does not transfer data to the host. When the requested sectors are verified, the onboard controller clears the BSY bit and issues an interrupt.

  • Page 68: Seek - 7Xh

    ATA C OMMAND LOCK AND Seek — 7Xh The Seek command seeks and picks up the head to the tracks specified in the task file. When the command is issued, the solid-state memory chips do not need to be formatted. After an appropriate amount of time, the DSC bit is set. Register Feature Sector Count...

  • Page 69: Set Features - Efh

    ATA C OMMAND LOCK AND Set Features — EFh The Set Features command allows the host to configure the feature set of the device according to the attributes listed in Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head Command Feature...

  • Page 70: Set Multiple Mode - C6H

    ATA C OMMAND LOCK AND Set Multiple Mode — C6h The Set Multiple Mode command allows the host to access the drive via Read Multiple and Write Multiple ATA commands. Additionally, the command sets the block count (i.e., the number of sectors within the block) for the Read/Write Multiple command.

  • Page 71: Set Sleep Mode - 99H, E6H

    ATA C OMMAND LOCK AND Set Sleep Mode — 99h, E6h The Set Sleep Mode command allows the host to set the device in sleep mode. When the onboard controller transitions to sleep mode, it clears the BSY bit and issues an interrupt. The device interface then becomes inactive. Sleep mode can be exited by issuing either a hardware or software reset.

  • Page 72: Standby - 96H, E2H

    ATA C OMMAND LOCK AND Standby — 96h, E2h When the Standby command is issued by the host, it transitions the device into standby mode. If the Sector Count register is set to a value other than 0h, the Auto Powerdown function is enabled and the device returns to Idle mode. Register Feature Sector Count...

  • Page 73: Standby Immediate - 94H, E0H

    ATA C OMMAND LOCK AND Standby Immediate — 94h, E0h When the Standby Immediate command is issued by the host, it transitions the device into standby mode. Table 50: Standby Immediate — 94h, E0h Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head...

  • Page 74: Write Buffer - E8H

    ATA C OMMAND LOCK AND Write Buffer — E8h The Write Buffer command allows the host to rewrite the contents of the 512- byte data buffer with the wanted data. Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head Command This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

  • Page 75: Write Dma - Cah

    ATA C OMMAND LOCK AND Write DMA — CAh The Write DMA command allows the host to write data using the DMA transfer protocol. Note: This function does not apply to SiliconDrive IIs that have DMA disabled. Register Feature Sector Count Sector Number Cylinder Low Cylinder High...

  • Page 76: Write Multiple - C5H

    ATA C OMMAND LOCK AND Write Multiple — C5h The Write Multiple command operates in the same manner as the Write Sector command. When issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer.

  • Page 77: Write Sector(S) - 30H, 31H

    ATA C OMMAND LOCK AND Write Sector(s) — 30h, 31h The Write Sector(s) command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. When issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors.

  • Page 78: Write Long Sector(S) - 32H, 33H

    ATA C OMMAND LOCK AND Write Long Sector(s) — 32h, 33h The Write Long Sector(s) command operates in the same manner as the Write Sector command — when issued, the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors. The DRQ bit is set at the beginning of a block transfer.

  • Page 79: Erase Sector(S) - C0H

    ATA C OMMAND LOCK AND Erase Sector(s) — C0h The Erase Sector(s) command is issued prior to the issuance of a Write Sector(s) or Write Multiple w/o Erase command. Register Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head Command This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

  • Page 80: Request Sense - 03H

    ATA C OMMAND LOCK AND Request Sense — 03h The Request Sense command identifies the extended error codes generated by the preceding ATA command. The Request Sense command must be issued immediately following the detection of an error via the Error register. Register Feature Sector Count...

  • Page 81: Translate Sector - 87H

    ATA C OMMAND LOCK AND Translate Sector — 87h The Translate Sector command is not currently supported by the SiliconSystems’ SiliconDrive II. If the host issues this command, the device responds with 0x00h in the data register. Register Feature Sector Count Sector Number Cylinder Low Cylinder High...

  • Page 82: Wear-Level - F5H

    ATA C OMMAND LOCK AND Wear-Level — F5h The Wear-Level command is supported as an NOP command for the purposes of backward compatibility with the ANSI AT attachment standard. This command sets the Sector Count register to 0x00h. Register Feature Sector Count Sector Number Cylinder Low...

  • Page 83: Write Multiple W/O Erase - Cdh

    ATA C OMMAND LOCK AND Write Multiple w/o Erase — CDh The Write Multiple w/o Erase command functions identically to the Write Multiple command, with the exception that the implied pre-erase (i.e., Erase Sector(s) command) is not issued prior to writing the sectors. Table 61: Write Multiple w/o Erase —...

  • Page 84: Write Sector(S) W/O Erase - 38H

    ATA C OMMAND LOCK AND Write Sector(s) w/o Erase — 38h The Write Sector(s) w/o Erase command functions similar to the Write Sector command, with the exception that the implied pre-erase (i.e., Erase Sector(s) command) is not issued prior to writing the sectors. Table 62: Write Sector(s) w/o Erase —...

  • Page 85: Write Verify - 3Ch

    ATA C OMMAND LOCK AND Write Verify — 3Ch The Write Verify command verifies each sector immediately after it is written. This command performs identically to the Write Sector(s) command, with the added feature of verifying each sector written. Register Feature Sector Count Sector Number...

  • Page 86: Sales And Support

    ALES AND UPPORT ALES AND UPPORT To order or obtain information on pricing and delivery, contact your SiliconSystems Sales Representative. UMBERING OMENCLATURE The following table defines the SiliconDrive II 2.5" PATA Drive part numbering scheme. SSD- Form Factor: D = 2.5" Drive SiliconSystems’...

  • Page 87: Rohs 6 Of 6 Product Labeling - Pb-Free Identification Label

    UMBERING HS 6 RODUCT The Pb-free identification label indicates that the enclosed components/ devices and/or assemblies do not contain any lead (i.e., they are lead-free, as defined in RoHS directive 2002/95/ED). The above symbol is on all RoHS 6 of 6 compliant product labels, as seen in AMPLE ABEL...

  • Page 88: Related Documentation

    ELATED OCUMENTATION ELATED OCUMENTATION For more information, visit SiliconSystems Sales Representative. SiliconDrive II Application-Specific Technology SiProtect SiSweep SiPurge SiliconSystems' performance tests, ratings, and product specifications are measured using specific computer systems and/or components and reflect the approximate performance of SiliconSystems’ products as measured by those tests. Any difference in system hardware or software design or configuration, as well as system use, may affect actual test results, ratings, and product specifications.

Table of Contents