Specification; Signal Descriptions; Table 8: Signal Descriptions - Silicon Systems SiliconDrive CF SSD-C08G(I)-3150 Datasheet

E S
LECTRICAL PECIFICATION
S D
IGNAL ESCRIPTIONS
Signal Name
A10-A0
A10-A0
(PC Card I/O
mode)
A2-A0
(True IDE mode)
BVD1
(PC Card memory
mode)
-STSCHG
(PC Card I/O
mode)
-PDIAG
(True IDE mode)
BVD2
(PC Card memory
mode)
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3150C-10DSR

Table 8: Signal Descriptions

Pin Type Description
8, 10, 11, I
12, 14, 15,
16, 17, 18,
19, 20
18, 19, 20 I
46 I/O
45 I/O
S S
ILICON YSTEMS
All unauthorized use and/or reproduction is prohibited.
P 6
AGE
SSD-C
XXX
These address lines along with the
-REG signal are used to select the
following:
• The I/O port address registers
within the SiliconDrive CF
• The memory-mapped port address
registers within the SiliconDrive CF
• A byte in the card's information
structure and its configuration
control and status registers
This signal is the same as the PC
Card Memory Mode signal.
In true IDE mode, only A[2:0] are used
to select the one of eight registers in
the Task File. The remaining address
lines should be grounded by the host.
This signal is asserted high, because
BVD1 is not supported.
This signal is asserted low to alert the
host to changes in the RDY/-BSY and
Write Protect states while the I/O
interface is configured. This signal's
use is controlled by the Card
Configuration and Status register.
In the true IDE mode, this input/output
is the Pass Diagnostic signal in the
Master/Slave handshake protocol.
This signal is asserted high, as BVD2
is not supported.
P
ROPRIETARY
(I)-3150 D S
ATA HEET
F 2, 2009
EBRUARY