Analog Inputs - Analog Devices EVAL-ADAQ7980SDZ User Manual

EVAL-ADAQ7980SDZ User Guide
Table 1 shows the configurations required for using the two on-
board references and an external reference.
Table 1. On-Board Reference Options Provided on the
EVAL-ADAQ7980SDZ
On-Board
Reference On-Board
Voltage (V) Reference Devices
5 ADR4550BRZ
3.3 ADR3433ARJZ
External Reference External device
Voltage
1 The J7 configuration is set to ensure the voltage input of the
within its specified range (<5.5 V).
The ADR4550BRZ and ADR3433ARJZ
VCM node, which can be used as a dc bias or common-mode
voltage for the analog-to-digital converter (ADC) driver. Figure 29
shows the circuitry generating VCM. See the Analog Inputs section
for more information on VCM operation.

ANALOG INPUTS

This section describes how to apply analog inputs to the
ADAQ7980SDZ.
The ADAQ7980 contains an ADC driver. The user has access to
the noninverting and inverting inputs and output of the ADC
driver (IN+, IN−, and AMP_OUT, respectively). This allows
configurability of the driver by means of jumper settings and
passive components. Figure 17 shows the ADC driver
connection diagram, including all relevant jumpers and passive
components for configuration.
J3
J2
A
VCM
A B
B
J1
B
VIN+
A
R21
R22
VCM
C25
Figure 17. Relevant Links and Components for Configuring the ADC Driver
The ADC input accepts unipolar signals between ground and
the voltage set by the integrated reference buffer (voltage on the
REF and REF_OUT pins). Therefore, the ADC driver outputs
must be limited to ground and the voltage on REF_OUT as
well. Because the signal is unipolar, the input signal must
include a dc offset component, typically to REF/2.
Link Settings
J7 at A
J9 at 1
J10 at 1
J7 at B
1
J9 at 3
J10 at 1
J10 at 3
ADR3433ARJZ
also supply the
EVAL-
C26
R20
R23
IN–
AMP_OUT
IN+
R24 C27
If the input source cannot supply the dc bias, a common mode
voltage generated on board (labeled VCM in Figure 17) can
connect to the noninverting input of the ADC driver through
the R
resistor. VCM is set to REF/2 by default. Use R
22
resistors to set VCM to another desired dc voltage. See the
Reference section for more information on VCM.
Table 2 outlines the link settings and passive components that
implement common ADC driver configurations.
Table 2. ADC Driver Configuration Settings
Configuration
Noninverting Unity-
Gain Buffer
is
Inverting with Level
Shift
Noninverting with
Nonunity Gain
Noninverting Unity-
Gain Buffer with
Level Shift
The EVAL-ADAQ7980SDZ
with the ADC driver in a unity-gain configuration. The dc
offset needed for unipolar signals can be provided either by the
signal source or by using the on-board dc offset VCM.
The analog inputs to the
SMA Connectors. The input circuit arrangement is controlled by
the settings of J1 to J3. The circuit not only allows different
configurations, input range scaling, and filtering, but also allows
adding a dc component. The analog input amplifiers are set as
unity-gain buffers by factory default. The amplifier positive rail is
driven from 7.5 V from U7 (ADP7118). The amplifier negative
rail is driven from −2.5 V, generated by U9 (ADP7182).
A differential output source can also drive the
ADAQ7980SDZ
be biased to the midscale (either internally or externally). The
P3 and P4 connectors and the R
termination of the signal source.
Rev. 0 | Page 9 of 30
Link
Settings Component
J1 at A Do not populate R
R
Do not populate R
R
Do not populate R
J1 at B, J2 at Select R
A, and J3 at A desired gain
Do not populate R
R
for desired dc
setting
J1 at A and Select R
J3 at B for desired gain
R
Do not populate R
and R
J1 at A Do not populate R
R
R
Select R
desired dc setting
is configured by factory default
EVAL-ADAQ7980SDZ
inputs as long as the output of the source can
/R voltage divider balance
18 19
UG-1060
and R
22 24
20
at 0 Ω
21
22
at 0 Ω
23
24
and R for
20 23
21
and R selected
22 24
and R
20 23
at 0 Ω
21
22
24
20
= R ≠ 0 Ω
21 22
at 0 Ω
23
for
24
are the P1 to P4
EVAL-