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Summary of Contents for Altera Stratix IV GT Edition
- Page 1 Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01052-1.1 Subscribe...
- Page 2 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
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Page 3: Table Of Contents
How to Contact Altera ........ - Page 4 Contents Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual...
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Page 5: Chapter 1. Overview
For information about setting up the Stratix IV GT transceiver signal integrity development board, and using the included software, refer to the Transceiver Signal Integrity Development Kit, Stratix IV GT Edition User Guide. General Description The Stratix IV GT transceiver signal integrity development board provides a hardware platform for evaluating the performance and signal integrity features of the ®... - Page 6 ■ 100-MHz clock trigger output to SMA connector ■ 644.53-MHz clock trigger output to SMA connector ■ 706.25-MHz clock trigger output to SMA connector ■ Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual...
- Page 7 ■ On/Off slide power switch ■ On-Board power measurement circuitry ■ Heat Sink and Fan ■ 40-mm heat sink and 5-V DC fan combo ■ November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual...
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Page 8: Development Board Block Diagram
2 Reset Buttons Backplane Connectors Buttons Transceivers Switches 8 User 8 User DIP Displays LEDs 6 User Rotary Buttons Switch 16 Char × 2 Line LCD Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... -
Page 9: Handling The Board
The Stratix IV GT transceiver signal integrity board must be stored between –40º C and 100º C. The recommended operating temperature is between 0º C and 55º C. November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual... - Page 10 1–6 Chapter 1: Overview Handling the Board Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual...
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Page 11: Chapter 2. Board Components
Stratix IV GT transceiver signal integrity development kit installation directory. For information about powering up the board and installing the development kit software, refer to the Transceiver Signal Integrity Development Kit, Stratix IV GT Edition User Guide. This chapter consists of the following sections: ■... -
Page 12: Board Overview
EP4S100G2F40I1N Stratix IV GT device in a 1517-pin FBGA package. Configuration, Status, and Setup Elements JTAG programming header for connecting an Altera USB-Blaster JTAG programming header dongle to program the FPGA and MAX II CPLD devices. MAX II JTAG configuration... - Page 13 Table 2–1. Stratix IV GT Transceiver Signal Integrity Development Board Components (Part 2 of 4) Board Reference Type Description Altera EPM1270256C3N, MAX II 256-pin CPLD for MAX II+FPP MAX II CPLD configuration. Indicates an FPGA over-temperature condition exists and a fan should Fan LED be attached to the FPGA and running.
- Page 14 Numonyx 48F4400P0VB00, 512-Mb flash memory. Components and Interfaces USB Type-B connector USB interface for embedded USB-Blaster. Altera EPM7064AETC44 MAX II CPLD device for embedded MAX II CPLD USB-Blaster circuitry. Ethernet RJ45 jack Halo HFJ11-1G02E RJ45 Ethernet jack with integrated magnetic.
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Page 15: Featured Device: Stratix Iv Gt Device
EP4S100G2F40I1N Stratix IV FPGA device (U33) in a 1517-pin FBGA package. For more information about the Stratix IV GT devices, refer to the Stratix IV Device Handbook. November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual... -
Page 16: I/O Resources
4 (1) GXBR0 GXBL0 Bank Name Number of I/Os Note to Figure 2–2: (1) There are two additional PMA-only transceiver channels in each transceiver bank. Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... - Page 17 Dedicated Configuration Pins CONFIG_DONE 2.5-V CMOS inout Dedicated Configuration Pins INIT_DONE 2.5-V CMOS output Dedicated Configuration Pins PGM[2:0] 2.5-V CMOS output Configuration Program Select Pins November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual...
- Page 18 Transceiver channel routed to a backplane connector J70. Six matched length GXB0 receive channels routed GXB0 Receive Channel Transceiver channel to a backplane connector J71. Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual...
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Page 19: Configuration, Status, And Setup Elements
Embedded USB-Blaster The embedded USB-Blaster is implemented using a Type-B USB connector (CN1), a Future Technologies FT245BL USB PHY device (U16), and an Altera EPM7064 MAX II CPLD (U17). This allows the configuration of the FPGA using a USB cable directly connected between the USB port on the board (CN1) and a USB port of a PC running the Quartus II software. -
Page 20: Fast Passive Parallel Download
CPLD shares the flash interface with the FPGA. The configuration program select jumper, PGMSEL, (J62) selects between two Programmer Object Files (.pof)—factory .pof or user .pof file stored in the flash. The FPP controller uses the Altera Parallel Flash Loader (PFL) megafunction to configure the FPGA by reading data from the flash and converting it to FPP format. -
Page 21: Jtag Programming Header
(J28). This header provides another method for configuring the FPGA (U33) using an Altera USB-Blaster with the Quartus II Programmer running on a PC. The MAX II JTAG configuration jumper (J26) allows the MAX II CPLD device to be removed from the JTAG chain so that the FPGA is the only device on the JTAG chain. -
Page 22: Board Jumpers
When a jumper is installed on pins 1-2, the fan is automatically controlled by the FPGA. When a jumper is installed on pins 2-3, the fan is always on. Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... - Page 23 Table 2–9. Spread Spectrum Configuration DIP Switch (SW2) Configuration Clock Frequency Spread Spectrum % 25 MHz Center ±25 100 MHz Down –0.50 125 MHz Down –0.75 200 MHz No spread spectrum November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual...
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Page 24: Clocks
Trigger (U24) (Y5) SMA (J23) CLKIN SMA (J19, J20) Table 2–10 shows the clock distribution for the Stratix IV GT transceiver signal integrity development board. Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... - Page 25 SMA J21 Y3 Trigger (Y3) 100 MHz U23 pin 3 SMA J22 Y4 Trigger (Y4) 706.25 MHz U24 pin 3 SMA J23 Y5 Trigger (Y5) November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual...
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Page 26: General User Input/Output
Board reset. This switch is not — U32 pin T2 RESETn debounced. CPU reset. This switch is not 10-kΩ pull-up U33 pin AW18 CPURSTn debounced. resistor to 2.5 V Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... -
Page 27: User Leds
J24 pin 6 LCD_EN LCD data/control signal U33 pin A18 J24 pin 4 LCD_D_Cn LCD write enable strobe U33 pin A17 J24 pin 5 LCD_Wen November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual... -
Page 28: Dip Switches
2.5-V CMOS U33 pin M14 U32 pin F16 F_AD12 U39 pin A5 Flash Address bus bit 13 2.5-V CMOS U33 pin K15 U32 pin D16 F_AD13 Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... - Page 29 Flash Write Protect 2.5-V CMOS U33 pin AT14 U32 pin T12 F_WPn U39 pin F7 Flash Busy 2.5-V CMOS U33 pin R14 U32 pin J14 F_BSYn November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual...
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Page 30: Components And Interfaces
The FPGA controls the fan based on the OVERTEMPn signal from the MAX1619, or the fan can be set to always ON. Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... - Page 31 Table 2–21. Temperature Sensor Component Reference Manufacturing Manufacturer Board Reference Description Manufacturer Part Number Website Dual temperature sensor with Maxim Integrated MAX1619MEE+T www.maxim-ic.com SMBus interface Products, Inc. November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual...
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Page 32: Power Measurement
Table 2–22. Power Rail Measurements Power Rail Voltage (V) Board Reference Rsense (Ω) and V 0.95 0.001 CCHIP 0.009 0.009 0.009 0.009 0.009 Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... -
Page 33: Ethernet Port
Board Manufacturing Manufacturer Description Manufacturer Reference Part Number Website Marvell 10/100/1000 Base-T Ethernet PHY 88E1111-B2-CAA1C000 www.marvell.com Semiconductor RJ45 with integrated magnetics Halo Electronics HFJ11-1G02ERL www.haloelectronics.com November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual... -
Page 34: Transceiver Channels
SMA connectors J38-J45 and J54-J61. In the left GXB2 block, two transmit and two receive channels are sent to SMA connectors J30-J37. Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... -
Page 35: Power
14 V to 20 V. The DC voltage is then stepped down to the various power rails used by the components on the board. The slide switch (SW1) is the board power switch. November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual... -
Page 36: Power Distribution System
Stratix IV GT Power (U6, U8) 1.2 V VCC_1.2V Other Power LT3080-1 @ 1.1 A Ethernet (U25) 1.8 V LTC3025-1 VCC_1.8V @ 0.5 A Flash (U38) Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual... -
Page 37: Banana Jacks And Fuses
Part Number Website Reference Johnson Banana jack and fuse 111-0702-001 www.johnsoncomponents.com Components F1, F2 for supplying external power to VCC core Littelfuse Inc. 154 010.DR www.littlefuse.com November 2011 Altera Corporation Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual... - Page 38 VCCT Littelfuse Inc. 154 002 www.littlefuse.com Johnson Banana jack 111-0703-001 www.johnsoncomponents.com Components — connected to board Littelfuse Inc. — www.littlefuse.com Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual...
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Page 39: Appendix A. Board Revision History
To determine which flash your board is using, refer to the device part number installed at U39. The single-die package is smaller than the dual-die version. For more information about the flash change and its application, refer to the Transceiver Signal Integrity Kit, Stratix IV GT Edition User Guide. November 2011 Altera Corporation... - Page 40 A–2 Appendix A: Board Revision History Single-Die Flash Version Differences Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual...
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Page 41: Additional Information
(software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels. - Page 42 The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation Stratix IV GT Edition Reference Manual...
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